1 /* 2 * Copyright (C) 2012 Vikram Narayananan 3 * <vikram186@gmail.com> 4 * (C) Copyright 2012,2015 Stephen Warren 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _BCM2835_GPIO_H_ 10 #define _BCM2835_GPIO_H_ 11 12 #ifdef CONFIG_BCM2836 13 #define BCM2835_GPIO_BASE 0x3f200000 14 #else 15 #define BCM2835_GPIO_BASE 0x20200000 16 #endif 17 #define BCM2835_GPIO_COUNT 54 18 19 #define BCM2835_GPIO_FSEL_MASK 0x7 20 #define BCM2835_GPIO_INPUT 0x0 21 #define BCM2835_GPIO_OUTPUT 0x1 22 #define BCM2835_GPIO_ALT0 0x4 23 #define BCM2835_GPIO_ALT1 0x5 24 #define BCM2835_GPIO_ALT2 0x6 25 #define BCM2835_GPIO_ALT3 0x7 26 #define BCM2835_GPIO_ALT4 0x3 27 #define BCM2835_GPIO_ALT5 0x2 28 29 #define BCM2835_GPIO_COMMON_BANK(gpio) ((gpio < 32) ? 0 : 1) 30 #define BCM2835_GPIO_COMMON_SHIFT(gpio) (gpio & 0x1f) 31 32 #define BCM2835_GPIO_FSEL_BANK(gpio) (gpio / 10) 33 #define BCM2835_GPIO_FSEL_SHIFT(gpio) ((gpio % 10) * 3) 34 35 struct bcm2835_gpio_regs { 36 u32 gpfsel[6]; 37 u32 reserved1; 38 u32 gpset[2]; 39 u32 reserved2; 40 u32 gpclr[2]; 41 u32 reserved3; 42 u32 gplev[2]; 43 u32 reserved4; 44 u32 gpeds[2]; 45 u32 reserved5; 46 u32 gpren[2]; 47 u32 reserved6; 48 u32 gpfen[2]; 49 u32 reserved7; 50 u32 gphen[2]; 51 u32 reserved8; 52 u32 gplen[2]; 53 u32 reserved9; 54 u32 gparen[2]; 55 u32 reserved10; 56 u32 gppud; 57 u32 gppudclk[2]; 58 }; 59 60 /** 61 * struct bcm2835_gpio_platdata - GPIO platform description 62 * 63 * @base: Base address of GPIO controller 64 */ 65 struct bcm2835_gpio_platdata { 66 unsigned long base; 67 }; 68 69 #endif /* _BCM2835_GPIO_H_ */ 70