1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2014 DENX Software Engineering 4 * Heiko Schocher <hs@denx.de> 5 * 6 * Based on: 7 * Copyright (C) 2013 Atmel Corporation 8 * Bo Shen <voice.shen@atmel.com> 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/arch/at91_common.h> 14 #include <asm/arch/at91sam9_matrix.h> 15 #include <asm/arch/at91_pit.h> 16 #include <asm/arch/at91_rstc.h> 17 #include <asm/arch/at91_wdt.h> 18 #include <asm/arch/clk.h> 19 #include <spl.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static void enable_ext_reset(void) 24 { 25 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; 26 27 writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); 28 } 29 30 void lowlevel_clock_init(void) 31 { 32 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 33 34 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { 35 /* Enable Main Oscillator */ 36 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); 37 38 /* Wait until Main Oscillator is stable */ 39 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) 40 ; 41 } 42 43 /* After stabilization, switch to Main Oscillator */ 44 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { 45 unsigned long tmp; 46 47 tmp = readl(&pmc->mckr); 48 tmp &= ~AT91_PMC_CSS; 49 tmp |= AT91_PMC_CSS_MAIN; 50 writel(tmp, &pmc->mckr); 51 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 52 ; 53 54 tmp &= ~AT91_PMC_PRES; 55 tmp |= AT91_PMC_PRES_1; 56 writel(tmp, &pmc->mckr); 57 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 58 ; 59 } 60 61 return; 62 } 63 64 void __weak matrix_init(void) 65 { 66 } 67 68 void __weak at91_spl_board_init(void) 69 { 70 } 71 72 void __weak spl_board_init(void) 73 { 74 } 75 76 void board_init_f(ulong dummy) 77 { 78 lowlevel_clock_init(); 79 #if !defined(CONFIG_AT91SAM9_WATCHDOG) 80 at91_disable_wdt(); 81 #endif 82 83 /* 84 * At this stage the main oscillator is supposed to be enabled 85 * PCK = MCK = MOSC 86 */ 87 at91_pllicpr_init(0x00); 88 89 /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ 90 at91_plla_init(CONFIG_SYS_AT91_PLLA); 91 92 /* PCK = PLLA = 2 * MCK */ 93 at91_mck_init(CONFIG_SYS_MCKR); 94 95 /* Switch MCK on PLLA output */ 96 at91_mck_init(CONFIG_SYS_MCKR_CSS); 97 98 #if defined(CONFIG_SYS_AT91_PLLB) 99 /* Configure PLLB */ 100 at91_pllb_init(CONFIG_SYS_AT91_PLLB); 101 #endif 102 103 /* Enable External Reset */ 104 enable_ext_reset(); 105 106 /* Initialize matrix */ 107 matrix_init(); 108 109 gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; 110 /* 111 * init timer long enough for using in spl. 112 */ 113 timer_init(); 114 115 /* enable clocks for all PIOs */ 116 #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) 117 at91_periph_clk_enable(ATMEL_ID_PIOAB); 118 at91_periph_clk_enable(ATMEL_ID_PIOCD); 119 #else 120 at91_periph_clk_enable(ATMEL_ID_PIOA); 121 at91_periph_clk_enable(ATMEL_ID_PIOB); 122 at91_periph_clk_enable(ATMEL_ID_PIOC); 123 #endif 124 125 #if defined(CONFIG_SPL_SERIAL_SUPPORT) 126 /* init console */ 127 at91_seriald_hw_init(); 128 preloader_console_init(); 129 #endif 130 131 mem_init(); 132 133 at91_spl_board_init(); 134 } 135