1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 262011840SMasahiro Yamada /* 362011840SMasahiro Yamada * (C) Copyright 2014 DENX Software Engineering 462011840SMasahiro Yamada * Heiko Schocher <hs@denx.de> 562011840SMasahiro Yamada * 662011840SMasahiro Yamada * Based on: 762011840SMasahiro Yamada * Copyright (C) 2013 Atmel Corporation 862011840SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 962011840SMasahiro Yamada */ 1062011840SMasahiro Yamada 1162011840SMasahiro Yamada #include <common.h> 1262011840SMasahiro Yamada #include <asm/io.h> 1362011840SMasahiro Yamada #include <asm/arch/at91_common.h> 1462011840SMasahiro Yamada #include <asm/arch/at91sam9_matrix.h> 1562011840SMasahiro Yamada #include <asm/arch/at91_pit.h> 1662011840SMasahiro Yamada #include <asm/arch/at91_rstc.h> 1762011840SMasahiro Yamada #include <asm/arch/at91_wdt.h> 1862011840SMasahiro Yamada #include <asm/arch/clk.h> 1962011840SMasahiro Yamada #include <spl.h> 2062011840SMasahiro Yamada 2162011840SMasahiro Yamada DECLARE_GLOBAL_DATA_PTR; 2262011840SMasahiro Yamada 2362011840SMasahiro Yamada static void enable_ext_reset(void) 2462011840SMasahiro Yamada { 2562011840SMasahiro Yamada struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; 2662011840SMasahiro Yamada 2762011840SMasahiro Yamada writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); 2862011840SMasahiro Yamada } 2962011840SMasahiro Yamada 3062011840SMasahiro Yamada void lowlevel_clock_init(void) 3162011840SMasahiro Yamada { 3262011840SMasahiro Yamada struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 3362011840SMasahiro Yamada 3462011840SMasahiro Yamada if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { 3562011840SMasahiro Yamada /* Enable Main Oscillator */ 3662011840SMasahiro Yamada writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); 3762011840SMasahiro Yamada 3862011840SMasahiro Yamada /* Wait until Main Oscillator is stable */ 3962011840SMasahiro Yamada while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) 4062011840SMasahiro Yamada ; 4162011840SMasahiro Yamada } 4262011840SMasahiro Yamada 4362011840SMasahiro Yamada /* After stabilization, switch to Main Oscillator */ 4462011840SMasahiro Yamada if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { 4562011840SMasahiro Yamada unsigned long tmp; 4662011840SMasahiro Yamada 4762011840SMasahiro Yamada tmp = readl(&pmc->mckr); 4862011840SMasahiro Yamada tmp &= ~AT91_PMC_CSS; 4962011840SMasahiro Yamada tmp |= AT91_PMC_CSS_MAIN; 5062011840SMasahiro Yamada writel(tmp, &pmc->mckr); 5162011840SMasahiro Yamada while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 5262011840SMasahiro Yamada ; 5362011840SMasahiro Yamada 5462011840SMasahiro Yamada tmp &= ~AT91_PMC_PRES; 5562011840SMasahiro Yamada tmp |= AT91_PMC_PRES_1; 5662011840SMasahiro Yamada writel(tmp, &pmc->mckr); 5762011840SMasahiro Yamada while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) 5862011840SMasahiro Yamada ; 5962011840SMasahiro Yamada } 6062011840SMasahiro Yamada 6162011840SMasahiro Yamada return; 6262011840SMasahiro Yamada } 6362011840SMasahiro Yamada 6462011840SMasahiro Yamada void __weak matrix_init(void) 6562011840SMasahiro Yamada { 6662011840SMasahiro Yamada } 6762011840SMasahiro Yamada 6862011840SMasahiro Yamada void __weak at91_spl_board_init(void) 6962011840SMasahiro Yamada { 7062011840SMasahiro Yamada } 7162011840SMasahiro Yamada 7241d41a93SBo Shen void __weak spl_board_init(void) 7341d41a93SBo Shen { 7441d41a93SBo Shen } 7541d41a93SBo Shen 7641d41a93SBo Shen void board_init_f(ulong dummy) 7762011840SMasahiro Yamada { 7862011840SMasahiro Yamada lowlevel_clock_init(); 7962011840SMasahiro Yamada at91_disable_wdt(); 8062011840SMasahiro Yamada 8162011840SMasahiro Yamada /* 8262011840SMasahiro Yamada * At this stage the main oscillator is supposed to be enabled 8362011840SMasahiro Yamada * PCK = MCK = MOSC 8462011840SMasahiro Yamada */ 85c43a72e8SWenyou Yang at91_pllicpr_init(0x00); 8662011840SMasahiro Yamada 8762011840SMasahiro Yamada /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ 8862011840SMasahiro Yamada at91_plla_init(CONFIG_SYS_AT91_PLLA); 8962011840SMasahiro Yamada 9062011840SMasahiro Yamada /* PCK = PLLA = 2 * MCK */ 9162011840SMasahiro Yamada at91_mck_init(CONFIG_SYS_MCKR); 9262011840SMasahiro Yamada 9362011840SMasahiro Yamada /* Switch MCK on PLLA output */ 9462011840SMasahiro Yamada at91_mck_init(CONFIG_SYS_MCKR_CSS); 9562011840SMasahiro Yamada 9662011840SMasahiro Yamada #if defined(CONFIG_SYS_AT91_PLLB) 9762011840SMasahiro Yamada /* Configure PLLB */ 9862011840SMasahiro Yamada at91_pllb_init(CONFIG_SYS_AT91_PLLB); 9962011840SMasahiro Yamada #endif 10062011840SMasahiro Yamada 10162011840SMasahiro Yamada /* Enable External Reset */ 10262011840SMasahiro Yamada enable_ext_reset(); 10362011840SMasahiro Yamada 10462011840SMasahiro Yamada /* Initialize matrix */ 10562011840SMasahiro Yamada matrix_init(); 10662011840SMasahiro Yamada 10762011840SMasahiro Yamada gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; 10862011840SMasahiro Yamada /* 10962011840SMasahiro Yamada * init timer long enough for using in spl. 11062011840SMasahiro Yamada */ 11162011840SMasahiro Yamada timer_init(); 11262011840SMasahiro Yamada 11362011840SMasahiro Yamada /* enable clocks for all PIOs */ 114ff255e83SBo Shen #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) 115d85e8914SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOAB); 116d85e8914SBo Shen at91_periph_clk_enable(ATMEL_ID_PIOCD); 117d85e8914SBo Shen #else 11862011840SMasahiro Yamada at91_periph_clk_enable(ATMEL_ID_PIOA); 11962011840SMasahiro Yamada at91_periph_clk_enable(ATMEL_ID_PIOB); 12062011840SMasahiro Yamada at91_periph_clk_enable(ATMEL_ID_PIOC); 121d85e8914SBo Shen #endif 12280402f34SHeiko Schocher 12380402f34SHeiko Schocher #if defined(CONFIG_SPL_SERIAL_SUPPORT) 12462011840SMasahiro Yamada /* init console */ 12562011840SMasahiro Yamada at91_seriald_hw_init(); 12662011840SMasahiro Yamada preloader_console_init(); 12780402f34SHeiko Schocher #endif 12862011840SMasahiro Yamada 12962011840SMasahiro Yamada mem_init(); 13062011840SMasahiro Yamada 13162011840SMasahiro Yamada at91_spl_board_init(); 13262011840SMasahiro Yamada } 133