1 /* 2 * (C) Copyright 2014 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * Based on: 6 * (C) Copyright 2007-2008 7 * Stelian Pop <stelian@popies.net> 8 * Lead Tech Design <www.leadtechdesign.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <asm/io.h> 15 #include <asm/arch/at91_common.h> 16 #include <asm/arch/at91sam9_sdramc.h> 17 #include <asm/arch/gpio.h> 18 19 int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) 20 { 21 struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; 22 unsigned int i; 23 24 /* SDRAM feature must be in the configuration register */ 25 writel(p->cr, ®->cr); 26 27 /* The SDRAM memory type must be set in the Memory Device Register */ 28 writel(p->mdr, ®->mdr); 29 30 /* 31 * The minimum pause of 200 us is provided to precede any single 32 * toggle 33 */ 34 for (i = 0; i < 1000; i++) 35 ; 36 37 /* A NOP command is issued to the SDRAM devices */ 38 writel(AT91_SDRAMC_MODE_NOP, ®->mr); 39 writel(0x00000000, sdram_address); 40 41 /* An All Banks Precharge command is issued to the SDRAM devices */ 42 writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); 43 writel(0x00000000, sdram_address); 44 45 for (i = 0; i < 10000; i++) 46 ; 47 48 /* Eight auto-refresh cycles are provided */ 49 for (i = 0; i < 8; i++) { 50 writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); 51 writel(0x00000001 + i, sdram_address + 4 + 4 * i); 52 } 53 54 /* 55 * A Mode Register set (MRS) cyscle is issued to program the 56 * SDRAM parameters(TCSR, PASR, DS) 57 */ 58 writel(AT91_SDRAMC_MODE_LMR, ®->mr); 59 writel(0xcafedede, sdram_address + 0x24); 60 61 /* 62 * The application must go into Normal Mode, setting Mode 63 * to 0 in the Mode Register and perform a write access at 64 * any location in the SDRAM. 65 */ 66 writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); 67 writel(0x00000000, sdram_address); /* Perform Normal mode */ 68 69 /* 70 * Write the refresh rate into the count field in the SDRAMC 71 * Refresh Timer Rgister. 72 */ 73 writel(p->tr, ®->tr); 74 75 return 0; 76 } 77