1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2014 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 * 6 * Based on: 7 * (C) Copyright 2007-2008 8 * Stelian Pop <stelian@popies.net> 9 * Lead Tech Design <www.leadtechdesign.com> 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/arch/at91_common.h> 15 #include <asm/arch/at91sam9_sdramc.h> 16 #include <asm/arch/gpio.h> 17 18 int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) 19 { 20 struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; 21 unsigned int i; 22 23 /* SDRAM feature must be in the configuration register */ 24 writel(p->cr, ®->cr); 25 26 /* The SDRAM memory type must be set in the Memory Device Register */ 27 writel(p->mdr, ®->mdr); 28 29 /* 30 * The minimum pause of 200 us is provided to precede any single 31 * toggle 32 */ 33 for (i = 0; i < 1000; i++) 34 ; 35 36 /* A NOP command is issued to the SDRAM devices */ 37 writel(AT91_SDRAMC_MODE_NOP, ®->mr); 38 writel(0x00000000, sdram_address); 39 40 /* An All Banks Precharge command is issued to the SDRAM devices */ 41 writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); 42 writel(0x00000000, sdram_address); 43 44 for (i = 0; i < 10000; i++) 45 ; 46 47 /* Eight auto-refresh cycles are provided */ 48 for (i = 0; i < 8; i++) { 49 writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); 50 writel(0x00000001 + i, sdram_address + 4 + 4 * i); 51 } 52 53 /* 54 * A Mode Register set (MRS) cyscle is issued to program the 55 * SDRAM parameters(TCSR, PASR, DS) 56 */ 57 writel(AT91_SDRAMC_MODE_LMR, ®->mr); 58 writel(0xcafedede, sdram_address + 0x24); 59 60 /* 61 * The application must go into Normal Mode, setting Mode 62 * to 0 in the Mode Register and perform a write access at 63 * any location in the SDRAM. 64 */ 65 writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); 66 writel(0x00000000, sdram_address); /* Perform Normal mode */ 67 68 /* 69 * Write the refresh rate into the count field in the SDRAMC 70 * Refresh Timer Rgister. 71 */ 72 writel(p->tr, ®->tr); 73 74 return 0; 75 } 76