1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 262011840SMasahiro Yamada /* 362011840SMasahiro Yamada * (C) Copyright 2007-2008 462011840SMasahiro Yamada * Stelian Pop <stelian@popies.net> 562011840SMasahiro Yamada * Lead Tech Design <www.leadtechdesign.com> 662011840SMasahiro Yamada * 762011840SMasahiro Yamada * (C) Copyright 2012 862011840SMasahiro Yamada * Markus Hubig <mhubig@imko.de> 962011840SMasahiro Yamada * IMKO GmbH <www.imko.de> 1062011840SMasahiro Yamada * 1162011840SMasahiro Yamada * Copyright (C) 2013 DENX Software Engineering, hs@denx.de 1262011840SMasahiro Yamada */ 1362011840SMasahiro Yamada 1462011840SMasahiro Yamada #include <common.h> 15e61ed48fSWenyou Yang #include <asm/hardware.h> 1662011840SMasahiro Yamada #include <asm/io.h> 1762011840SMasahiro Yamada #include <linux/sizes.h> 1862011840SMasahiro Yamada #include <asm/arch/at91_rstc.h> 1962011840SMasahiro Yamada #include <watchdog.h> 2062011840SMasahiro Yamada at91_phy_reset(void)2162011840SMasahiro Yamadavoid at91_phy_reset(void) 2262011840SMasahiro Yamada { 2362011840SMasahiro Yamada unsigned long erstl; 2462011840SMasahiro Yamada unsigned long start = get_timer(0); 2562011840SMasahiro Yamada unsigned long const timeout = 1000; /* 1000ms */ 2662011840SMasahiro Yamada at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; 2762011840SMasahiro Yamada 2862011840SMasahiro Yamada erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; 2962011840SMasahiro Yamada 3062011840SMasahiro Yamada /* 3162011840SMasahiro Yamada * Need to reset PHY -> 500ms reset 3262011840SMasahiro Yamada * Reset PHY by pulling the NRST line for 500ms to low. To do so 3362011840SMasahiro Yamada * disable user reset for low level on NRST pin and poll the NRST 3462011840SMasahiro Yamada * level in reset status register. 3562011840SMasahiro Yamada */ 3662011840SMasahiro Yamada writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | 3762011840SMasahiro Yamada AT91_RSTC_MR_URSTEN, &rstc->mr); 3862011840SMasahiro Yamada 3962011840SMasahiro Yamada writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); 4062011840SMasahiro Yamada 4162011840SMasahiro Yamada /* Wait for end of hardware reset */ 4262011840SMasahiro Yamada while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { 4362011840SMasahiro Yamada /* avoid shutdown by watchdog */ 4462011840SMasahiro Yamada WATCHDOG_RESET(); 4562011840SMasahiro Yamada mdelay(10); 4662011840SMasahiro Yamada 4762011840SMasahiro Yamada /* timeout for not getting stuck in an endless loop */ 4862011840SMasahiro Yamada if (get_timer(start) >= timeout) { 4962011840SMasahiro Yamada puts("*** ERROR: Timeout waiting for PHY reset!\n"); 5062011840SMasahiro Yamada break; 5162011840SMasahiro Yamada } 5262011840SMasahiro Yamada }; 5362011840SMasahiro Yamada 5462011840SMasahiro Yamada /* Restore NRST value */ 5562011840SMasahiro Yamada writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); 5662011840SMasahiro Yamada } 57