1 /* 2 * Copyright (C) 2012 Atmel Corporation. 3 * 4 * Static Memory Controllers (SMC) - System peripherals registers. 5 * Based on SAMA5D3 datasheet. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef SAMA5D3_SMC_H 11 #define SAMA5D3_SMC_H 12 13 #ifdef __ASSEMBLY__ 14 #define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600) 15 #define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604) 16 #define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608) 17 #define AT91_ASM_SMC_TIMINGS0 (ATMEL_BASE_SMC + 0x60c) 18 #define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x610) 19 #else 20 struct at91_cs { 21 u32 setup; /* 0x600 SMC Setup Register */ 22 u32 pulse; /* 0x604 SMC Pulse Register */ 23 u32 cycle; /* 0x608 SMC Cycle Register */ 24 u32 timings; /* 0x60C SMC Cycle Register */ 25 u32 mode; /* 0x610 SMC Mode Register */ 26 }; 27 28 struct at91_smc { 29 u32 reserved[384]; 30 struct at91_cs cs[4]; 31 }; 32 #endif /* __ASSEMBLY__ */ 33 34 #define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 35 #define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 36 #define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 37 #define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 38 39 #define AT91_SMC_PULSE_NWE(x) (x & 0x3f) 40 #define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8) 41 #define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16) 42 #define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24) 43 44 #define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 45 #define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 46 47 #define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf) 48 #define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4) 49 #define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8) 50 #define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12) 51 #define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16) 52 #define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24) 53 #define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28) 54 #define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31) 55 56 #define AT91_SMC_MODE_RM_NCS 0x00000000 57 #define AT91_SMC_MODE_RM_NRD 0x00000001 58 #define AT91_SMC_MODE_WM_NCS 0x00000000 59 #define AT91_SMC_MODE_WM_NWE 0x00000002 60 61 #define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 62 #define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 63 #define AT91_SMC_MODE_EXNW_READY 0x00000030 64 65 #define AT91_SMC_MODE_BAT 0x00000100 66 #define AT91_SMC_MODE_DBW_8 0x00000000 67 #define AT91_SMC_MODE_DBW_16 0x00001000 68 #define AT91_SMC_MODE_DBW_32 0x00002000 69 #define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 70 #define AT91_SMC_MODE_TDF 0x00100000 71 #define AT91_SMC_MODE_PMEN 0x01000000 72 #define AT91_SMC_MODE_PS_4 0x00000000 73 #define AT91_SMC_MODE_PS_8 0x10000000 74 #define AT91_SMC_MODE_PS_16 0x20000000 75 #define AT91_SMC_MODE_PS_32 0x30000000 76 77 #endif 78