1 /*
2  * Chip-specific header file for the SAMA5D2 SoC
3  *
4  * Copyright (C) 2015 Atmel
5  *		      Wenyou Yang <wenyou.yang@atmel.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __SAMA5D2_H
11 #define __SAMA5D2_H
12 
13 /*
14  * definitions to be used in other places
15  */
16 #define CONFIG_AT91FAMILY	/* It's a member of AT91 */
17 
18 /*
19  * Peripheral identifiers/interrupts.
20  */
21 #define ATMEL_ID_FIQ		0	/* FIQ Interrupt ID */
22 /* 1 */
23 #define ATMEL_ID_ARM		2	/* Performance Monitor Unit */
24 #define ATMEL_ID_PIT		3	/* Periodic Interval Timer Interrupt */
25 #define ATMEL_ID_WDT		4	/* Watchdog Timer Interrupt */
26 #define ATMEL_ID_GMAC		5	/* Ethernet MAC */
27 #define ATMEL_ID_XDMAC0		6	/* DMA Controller 0 */
28 #define ATMEL_ID_XDMAC1		7	/* DMA Controller 1 */
29 #define ATMEL_ID_ICM		8	/* Integrity Check Monitor */
30 #define ATMEL_ID_AES		9	/* Advanced Encryption Standard */
31 #define ATMEL_ID_AESB		10	/* AES bridge */
32 #define ATMEL_ID_TDES		11	/* Triple Data Encryption Standard */
33 #define ATMEL_ID_SHA		12	/* SHA Signature */
34 #define ATMEL_ID_MPDDRC		13	/* MPDDR Controller */
35 #define ATMEL_ID_MATRIX1	14	/* H32MX, 32-bit AHB Matrix */
36 #define ATMEL_ID_MATRIX0	15	/* H64MX, 64-bit AHB Matrix */
37 #define ATMEL_ID_SECUMOD	16	/* Secure Module */
38 #define ATMEL_ID_HSMC		17	/* Multi-bit ECC interrupt */
39 #define ATMEL_ID_PIOA		18	/* Parallel I/O Controller A */
40 #define ATMEL_ID_FLEXCOM0	19	/* FLEXCOM0 */
41 #define ATMEL_ID_FLEXCOM1	20	/* FLEXCOM1 */
42 #define ATMEL_ID_FLEXCOM2	21	/* FLEXCOM2 */
43 #define ATMEL_ID_FLEXCOM3	22	/* FLEXCOM3 */
44 #define ATMEL_ID_FLEXCOM4	23	/* FLEXCOM4 */
45 #define ATMEL_ID_UART0		24	/* UART0 */
46 #define ATMEL_ID_UART1		25	/* UART1 */
47 #define ATMEL_ID_UART2		26	/* UART2 */
48 #define ATMEL_ID_UART3		27	/* UART3 */
49 #define ATMEL_ID_UART4		28	/* UART4 */
50 #define ATMEL_ID_TWIHS0		29	/* Two-wire Interface 0 */
51 #define ATMEL_ID_TWIHS1		30	/* Two-wire Interface 1 */
52 #define ATMEL_ID_SDMMC0		31	/* Secure Data Memory Card Controller 0 */
53 #define ATMEL_ID_SDMMC1		32	/* Secure Data Memory Card Controller 1 */
54 #define ATMEL_ID_SPI0		33	/* Serial Peripheral Interface 0 */
55 #define ATMEL_ID_SPI1		34	/* Serial Peripheral Interface 1 */
56 #define ATMEL_ID_TC0		35	/* Timer Counter 0 (ch.0,1,2) */
57 #define ATMEL_ID_TC1		36	/* Timer Counter 1 (ch.3,4,5) */
58 /* 37 */
59 #define ATMEL_ID_PWM		38	/* PWMController0 (ch. 0,1,2,3) */
60 /* 39 */
61 #define ATMEL_ID_ADC		40	/* Touch Screen ADC Controller */
62 #define ATMEL_ID_UHPHS		41	/* USB Host High Speed */
63 #define ATMEL_ID_UDPHS		42	/* USB Device High Speed */
64 #define ATMEL_ID_SSC0		43	/* Serial Synchronous Controller 0 */
65 #define ATMEL_ID_SSC1		44	/* Serial Synchronous Controller 1 */
66 #define ATMEL_ID_LCDC		45	/* LCD Controller */
67 #define ATMEL_ID_ISI		46	/* Image Sensor Controller, for A5D2, named after ISC */
68 #define ATMEL_ID_TRNG		47	/* True Random Number Generator */
69 #define ATMEL_ID_PDMIC		48	/* PDM Interface Controller */
70 #define ATMEL_ID_AIC_IRQ	49	/* IRQ Interrupt ID */
71 #define ATMEL_ID_SFC		50	/* Fuse Controller */
72 #define ATMEL_ID_SECURAM	51	/* Secure RAM */
73 #define ATMEL_ID_QSPI0		52	/* QSPI0 */
74 #define ATMEL_ID_QSPI1		53	/* QSPI1 */
75 #define ATMEL_ID_I2SC0		54	/* Inter-IC Sound Controller 0 */
76 #define ATMEL_ID_I2SC1		55	/* Inter-IC Sound Controller 1 */
77 #define ATMEL_ID_CAN0_INT0	56	/* MCAN 0 Interrupt0 */
78 #define ATMEL_ID_CAN1_INT0	57	/* MCAN 1 Interrupt0 */
79 /* 58 */
80 #define ATMEL_ID_CLASSD		59	/* Audio Class D Amplifier */
81 #define ATMEL_ID_SFR		60	/* Special Function Register */
82 #define ATMEL_ID_SAIC		61	/* Secured AIC */
83 #define ATMEL_ID_AIC		62	/* Advanced Interrupt Controller */
84 #define ATMEL_ID_L2CC		63	/* L2 Cache Controller */
85 #define ATMEL_ID_CAN0_INT1	64	/* MCAN 0 Interrupt1 */
86 #define ATMEL_ID_CAN1_INT1	65	/* MCAN 1 Interrupt1 */
87 #define ATMEL_ID_GMAC_Q1	66	/* GMAC Queue 1 Interrupt */
88 #define ATMEL_ID_GMAC_Q2	67	/* GMAC Queue 2 Interrupt */
89 #define ATMEL_ID_PIOB		68	/* Parallel I/O Controller B */
90 #define ATMEL_ID_PIOC		69	/* Parallel I/O Controller C */
91 #define ATMEL_ID_PIOD		70	/* Parallel I/O Controller D */
92 #define ATMEL_ID_SDMMC0_TIMER	71	/* Secure Data Memory Card Controller 0 (TIMER) */
93 #define ATMEL_ID_SDMMC1_TIMER	72	/* Secure Data Memory Card Controller 1 (TIMER) */
94 /* 73 */
95 #define ATMEL_ID_SYS		74	/* System Controller Interrupt */
96 #define ATMEL_ID_ACC		75	/* Analog Comparator */
97 #define ATMEL_ID_RXLP		76	/* UART Low-Power */
98 #define ATMEL_ID_SFRBU		77	/* Special Function Register BackUp */
99 #define ATMEL_ID_CHIPID		78	/* Chip ID */
100 
101 /*
102  * User Peripherals physical base addresses.
103  */
104 #define ATMEL_BASE_LCDC		0xf0000000
105 #define ATMEL_BASE_XDMAC1	0xf0004000
106 #define ATMEL_BASE_MPDDRC	0xf000c000
107 #define ATMEL_BASE_XDMAC0	0xf0010000
108 #define ATMEL_BASE_PMC		0xf0014000
109 #define ATMEL_BASE_MATRIX0	0xf0018000
110 #define ATMEL_BASE_QSPI0	0xf0020000
111 #define ATMEL_BASE_QSPI1	0xf0024000
112 #define ATMEL_BASE_SPI0		0xf8000000
113 #define ATMEL_BASE_GMAC		0xf8008000
114 #define ATMEL_BASE_TC0		0xf800c000
115 #define ATMEL_BASE_TC1		0xf8010000
116 #define ATMEL_BASE_HSMC		0xf8014000
117 #define ATMEL_BASE_UART0	0xf801c000
118 #define ATMEL_BASE_UART1	0xf8020000
119 #define ATMEL_BASE_UART2	0xf8024000
120 #define ATMEL_BASE_TWI0		0xf8028000
121 #define ATMEL_BASE_SFR		0xf8030000
122 #define ATMEL_BASE_SYSC		0xf8048000
123 #define ATMEL_BASE_SPI1		0xfc000000
124 #define ATMEL_BASE_UART3	0xfc008000
125 #define ATMEL_BASE_UART4	0xfc00c000
126 #define ATMEL_BASE_TWI1		0xfc028000
127 #define ATMEL_BASE_UDPHS	0xfc02c000
128 
129 #define ATMEL_BASE_PIOA		0xfc038000
130 #define ATMEL_BASE_MATRIX1	0xfc03c000
131 
132 #define ATMEL_CHIPID_CIDR	0xfc069000
133 #define ATMEL_CHIPID_EXID	0xfc069004
134 
135 /*
136  * Address Memory Space
137  */
138 #define ATMEL_BASE_DDRCS		0x20000000
139 #define ATMEL_BASE_QSPI0_AES_MEM	0x90000000
140 #define ATMEL_BASE_QSPI1_AES_MEM	0x98000000
141 #define ATMEL_BASE_SDMMC0		0xa0000000
142 #define ATMEL_BASE_SDMMC1		0xb0000000
143 #define ATMEL_BASE_QSPI0_MEM		0xd0000000
144 #define ATMEL_BASE_QSPI1_MEM		0xd8000000
145 
146 /*
147  * Internal Memories
148  */
149 #define ATMEL_BASE_UDPHS_FIFO	0x00300000	/* USB Device HS controller */
150 #define ATMEL_BASE_OHCI		0x00400000	/* USB Host controller (OHCI) */
151 #define ATMEL_BASE_EHCI		0x00500000	/* USB Host controller (EHCI) */
152 
153 /*
154  * SYSC Spawns
155  */
156 #define ATMEL_BASE_RSTC		ATMEL_BASE_SYSC
157 #define ATMEL_BASE_SHDWC	(ATMEL_BASE_SYSC + 0x10)
158 #define ATMEL_BASE_PIT		(ATMEL_BASE_SYSC + 0x30)
159 #define ATMEL_BASE_WDT		(ATMEL_BASE_SYSC + 0x40)
160 #define ATMEL_BASE_SCKC		(ATMEL_BASE_SYSC + 0x50)
161 #define ATMEL_BASE_RTC		(ATMEL_BASE_SYSC + 0xb0)
162 
163 /*
164  * Other misc definitions
165  */
166 #define ATMEL_BASE_PMECC	(ATMEL_BASE_HSMC + 0x70)
167 #define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_HSMC + 0x500)
168 
169 #define ATMEL_BASE_PIOB		(ATMEL_BASE_PIOA + 0x40)
170 #define ATMEL_BASE_PIOC		(ATMEL_BASE_PIOB + 0x40)
171 #define ATMEL_BASE_PIOD		(ATMEL_BASE_PIOC + 0x40)
172 
173 #define ATMEL_PIO_PORTS		4
174 #define CPU_HAS_PCR
175 #define CPU_HAS_H32MXDIV
176 
177 /* AICREDIR Unlock Key */
178 #define ATMEL_SFR_AICREDIR_KEY		0xB6D81C4D
179 
180 /* MATRIX0(H64MX) slave id definitions */
181 #define H64MX_SLAVE_AXIMX_BRIDGE	0	/* Bridge from H64MX to AXIMX */
182 #define H64MX_SLAVE_PERIPH_BRIDGE	1	/* H64MX Peripheral Bridge */
183 #define H64MX_SLAVE_DDRC_PORT0		2	/* DDR2 Port0-AESOTF */
184 #define H64MX_SLAVE_DDRC_PORT1		3	/* DDR2 Port1 */
185 #define H64MX_SLAVE_DDRC_PORT2		4	/* DDR2 Port2 */
186 #define H64MX_SLAVE_DDRC_PORT3		5	/* DDR2 Port3 */
187 #define H64MX_SLAVE_DDRC_PORT4		6	/* DDR2 Port4 */
188 #define H64MX_SLAVE_DDRC_PORT5		7	/* DDR2 Port5 */
189 #define H64MX_SLAVE_DDRC_PORT6		8	/* DDR2 Port6 */
190 #define H64MX_SLAVE_DDRC_PORT7		9	/* DDR2 Port7 */
191 #define H64MX_SLAVE_SRAM		10	/* Internal SRAM 128K */
192 #define H64MX_SLAVE_CACHE_L2		11	/* Internal SRAM 128K(L2) */
193 #define H64MX_SLAVE_QSPI0		12	/* QSPI0 */
194 #define H64MX_SLAVE_QSPI1		13	/* QSPI1 */
195 #define H64MX_SLAVE_AESB		14	/* AESB */
196 
197 /* MATRIX1(H32MX) slave id definitions */
198 #define H32MX_SLAVE_H64MX_BRIDGE	0	/* Bridge from H32MX to H64MX */
199 #define H32MX_SLAVE_PERIPH_BRIDGE0	1	/* H32MX Peripheral Bridge 0 */
200 #define H32MX_SLAVE_PERIPH_BRIDGE1	2	/* H32MX Peripheral Bridge 1 */
201 #define H32MX_SLAVE_EBI			3	/* External Bus Interface */
202 #define H32MX_SLAVE_NFC_CMD		3	/* NFC command Register */
203 #define H32MX_SLAVE_NFC_SRAM		4	/* NFC SRAM */
204 #define H32MX_SLAVE_USB			5	/* USB Device & Host */
205 
206 /* SAMA5D2 series chip id definitions */
207 #define ARCH_ID_SAMA5D2		0x8a5c08c0
208 #define ARCH_EXID_SAMA5D21CU	0x0000005a
209 #define ARCH_EXID_SAMA5D22CU	0x00000059
210 #define ARCH_EXID_SAMA5D22CN	0x00000069
211 #define ARCH_EXID_SAMA5D23CU	0x00000058
212 #define ARCH_EXID_SAMA5D24CX	0x00000004
213 #define ARCH_EXID_SAMA5D24CU	0x00000014
214 #define ARCH_EXID_SAMA5D26CU	0x00000012
215 #define ARCH_EXID_SAMA5D27CU	0x00000011
216 #define ARCH_EXID_SAMA5D27CN	0x00000021
217 #define ARCH_EXID_SAMA5D28CU	0x00000010
218 #define ARCH_EXID_SAMA5D28CN	0x00000020
219 
220 #define cpu_is_sama5d2()	(get_chip_id() == ARCH_ID_SAMA5D2)
221 
222 /* PIT Timer(PIT_PIIR) */
223 #define CONFIG_SYS_TIMER_COUNTER	0xf804803c
224 
225 /* No PMECC Galois table in ROM */
226 #define NO_GALOIS_TABLE_IN_ROM
227 
228 #ifndef __ASSEMBLY__
229 unsigned int get_chip_id(void);
230 unsigned int get_extension_chip_id(void);
231 unsigned int has_lcdc(void);
232 char *get_cpu_name(void);
233 #endif
234 
235 #endif
236