1 /*
2  * Special Function Register (SFR)
3  *
4  * Copyright (C) 2014 Atmel
5  *		      Bo Shen <voice.shen@atmel.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __SAMA5_SFR_H
11 #define __SAMA5_SFR_H
12 
13 struct atmel_sfr {
14 	u32 reserved1;	/* 0x00 */
15 	u32 ddrcfg;	/* 0x04: DDR Configuration Register */
16 	u32 reserved2;	/* 0x08 */
17 	u32 reserved3;	/* 0x0c */
18 	u32 ohciicr;	/* 0x10: OHCI Interrupt Configuration Register */
19 	u32 ohciisr;	/* 0x14: OHCI Interrupt Status Register */
20 	u32 reserved4[4];	/* 0x18 ~ 0x24 */
21 	u32 secure;		/* 0x28: Security Configuration Register */
22 	u32 reserved5[5];	/* 0x2c ~ 0x3c */
23 	u32 ebicfg;		/* 0x40: EBI Configuration Register */
24 	u32 reserved6[2];	/* 0x44 ~ 0x48 */
25 	u32 sn0;		/* 0x4c */
26 	u32 sn1;		/* 0x50 */
27 	u32 aicredir;	/* 0x54 */
28 	u32 l2cc_hramc;	/* 0x58 */
29 };
30 
31 /* Register Mapping*/
32 #define AT91_SFR_UTMICKTRIM	0x30	/* UTMI Clock Trimming Register */
33 
34 /* Bit field in DDRCFG */
35 #define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
36 #define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
37 
38 /* Bit field in EBICFG */
39 #define AT91_SFR_EBICFG_DRIVE0		(0x3 << 0)
40 #define AT91_SFR_EBICFG_DRIVE0_LOW		(0x0 << 0)
41 #define AT91_SFR_EBICFG_DRIVE0_MEDIUM		(0x2 << 0)
42 #define AT91_SFR_EBICFG_DRIVE0_HIGH		(0x3 << 0)
43 #define AT91_SFR_EBICFG_PULL0		(0x3 << 2)
44 #define AT91_SFR_EBICFG_PULL0_UP		(0x0 << 2)
45 #define AT91_SFR_EBICFG_PULL0_NONE		(0x1 << 2)
46 #define AT91_SFR_EBICFG_PULL0_DOWN		(0x3 << 2)
47 #define AT91_SFR_EBICFG_SCH0		(0x1 << 4)
48 #define AT91_SFR_EBICFG_SCH0_OFF		(0x0 << 4)
49 #define AT91_SFR_EBICFG_SCH0_ON			(0x1 << 4)
50 #define AT91_SFR_EBICFG_DRIVE1		(0x3 << 8)
51 #define AT91_SFR_EBICFG_DRIVE1_LOW		(0x0 << 8)
52 #define AT91_SFR_EBICFG_DRIVE1_MEDIUM		(0x2 << 8)
53 #define AT91_SFR_EBICFG_DRIVE1_HIGH		(0x3 << 8)
54 #define AT91_SFR_EBICFG_PULL1		(0x3 << 10)
55 #define AT91_SFR_EBICFG_PULL1_UP		(0x0 << 10)
56 #define AT91_SFR_EBICFG_PULL1_NONE		(0x1 << 10)
57 #define AT91_SFR_EBICFG_PULL1_DOWN		(0x3 << 10)
58 #define AT91_SFR_EBICFG_SCH1		(0x1 << 12)
59 #define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
60 #define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
61 
62 #define AT91_UTMICKTRIM_FREQ		GENMASK(1, 0)
63 
64 /* Bit field in AICREDIR */
65 #define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
66 
67 #endif
68