1 /* 2 * Bus Matrix header file for the SAMA5 family 3 * 4 * Copyright (C) 2014 Atmel 5 * Bo Shen <voice.shen@atmel.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __SAMA5_MATRIX_H 11 #define __SAMA5_MATRIX_H 12 13 struct atmel_matrix { 14 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */ 15 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */ 16 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */ 17 u32 res1[20]; /* 0x100 ~ 0x14c */ 18 u32 meier; /* 0x150: Master Error Interrupt Enable Register */ 19 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */ 20 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */ 21 u32 mesr; /* 0x15c: Master Error Status Register */ 22 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */ 23 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */ 24 u32 wpmr; /* 0x1E4: Write Protection Mode Register */ 25 u32 wpsr; /* 0x1E8: Write Protection Status Register */ 26 u32 res3[5]; /* 0x1EC ~ 0x1FC */ 27 u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */ 28 u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */ 29 u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */ 30 u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */ 31 }; 32 33 /* Bit field in WPMR */ 34 #define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400 35 #define ATMEL_MATRIX_WPMR_WPEN 0x00000001 36 37 #endif 38