1 /*
2  * (C) Copyright 2007
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 #ifndef __ASM_ARM_ARCH_CLK_H__
10 #define __ASM_ARM_ARCH_CLK_H__
11 
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/global_data.h>
15 
16 #define GCK_CSS_SLOW_CLK	0
17 #define GCK_CSS_MAIN_CLK	1
18 #define GCK_CSS_PLLA_CLK	2
19 #define GCK_CSS_UPLL_CLK	3
20 #define GCK_CSS_MCK_CLK		4
21 #define GCK_CSS_AUDIO_CLK	5
22 
23 static inline unsigned long get_cpu_clk_rate(void)
24 {
25 	DECLARE_GLOBAL_DATA_PTR;
26 	return gd->arch.cpu_clk_rate_hz;
27 }
28 
29 static inline unsigned long get_main_clk_rate(void)
30 {
31 	DECLARE_GLOBAL_DATA_PTR;
32 	return gd->arch.main_clk_rate_hz;
33 }
34 
35 static inline unsigned long get_mck_clk_rate(void)
36 {
37 	DECLARE_GLOBAL_DATA_PTR;
38 	return gd->arch.mck_rate_hz;
39 }
40 
41 static inline unsigned long get_plla_clk_rate(void)
42 {
43 	DECLARE_GLOBAL_DATA_PTR;
44 	return gd->arch.plla_rate_hz;
45 }
46 
47 static inline unsigned long get_pllb_clk_rate(void)
48 {
49 	DECLARE_GLOBAL_DATA_PTR;
50 	return gd->arch.pllb_rate_hz;
51 }
52 
53 static inline u32 get_pllb_init(void)
54 {
55 	DECLARE_GLOBAL_DATA_PTR;
56 	return gd->arch.at91_pllb_usb_init;
57 }
58 
59 #ifdef CPU_HAS_H32MXDIV
60 static inline unsigned int get_h32mxdiv(void)
61 {
62 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
63 
64 	return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
65 }
66 #else
67 static inline unsigned int get_h32mxdiv(void)
68 {
69 	return 0;
70 }
71 #endif
72 
73 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
74 {
75 	if (get_h32mxdiv())
76 		return get_mck_clk_rate() / 2;
77 	else
78 		return get_mck_clk_rate();
79 }
80 
81 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
82 {
83 	if (get_h32mxdiv())
84 		return get_mck_clk_rate() / 2;
85 	else
86 		return get_mck_clk_rate();
87 }
88 
89 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
90 {
91 	return get_mck_clk_rate();
92 }
93 
94 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
95 {
96 	if (get_h32mxdiv())
97 		return get_mck_clk_rate() / 2;
98 	else
99 		return get_mck_clk_rate();
100 }
101 
102 static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
103 {
104 	if (get_h32mxdiv())
105 		return get_mck_clk_rate() / 2;
106 	else
107 		return get_mck_clk_rate();
108 }
109 
110 static inline unsigned long get_mci_clk_rate(void)
111 {
112 	if (get_h32mxdiv())
113 		return get_mck_clk_rate() / 2;
114 	else
115 		return get_mck_clk_rate();
116 }
117 
118 static inline unsigned long get_pit_clk_rate(void)
119 {
120 	if (get_h32mxdiv())
121 		return get_mck_clk_rate() / 2;
122 	else
123 		return get_mck_clk_rate();
124 }
125 
126 int at91_clock_init(unsigned long main_clock);
127 void at91_periph_clk_enable(int id);
128 void at91_periph_clk_disable(int id);
129 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
130 u32 at91_get_periph_generated_clk(u32 id);
131 void at91_system_clk_enable(int sys_clk);
132 void at91_system_clk_disable(int sys_clk);
133 int at91_upll_clk_enable(void);
134 int at91_upll_clk_disable(void);
135 void at91_usb_clk_init(u32 value);
136 int at91_pllb_clk_enable(u32 pllbr);
137 int at91_pllb_clk_disable(void);
138 void at91_pllicpr_init(u32 icpr);
139 
140 #endif /* __ASM_ARM_ARCH_CLK_H__ */
141