1 /*
2  * (C) Copyright 2007
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 #ifndef __ASM_ARM_ARCH_CLK_H__
10 #define __ASM_ARM_ARCH_CLK_H__
11 
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/at91_pmc.h>
14 #include <asm/global_data.h>
15 
16 #define GCK_CSS_SLOW_CLK	0
17 #define GCK_CSS_MAIN_CLK	1
18 #define GCK_CSS_PLLA_CLK	2
19 #define GCK_CSS_UPLL_CLK	3
20 #define GCK_CSS_MCK_CLK		4
21 #define GCK_CSS_AUDIO_CLK	5
22 
23 #define AT91_UTMI_PLL_CLK_FREQ	480000000
24 
25 static inline unsigned long get_cpu_clk_rate(void)
26 {
27 	DECLARE_GLOBAL_DATA_PTR;
28 	return gd->arch.cpu_clk_rate_hz;
29 }
30 
31 static inline unsigned long get_main_clk_rate(void)
32 {
33 	DECLARE_GLOBAL_DATA_PTR;
34 	return gd->arch.main_clk_rate_hz;
35 }
36 
37 static inline unsigned long get_mck_clk_rate(void)
38 {
39 	DECLARE_GLOBAL_DATA_PTR;
40 	return gd->arch.mck_rate_hz;
41 }
42 
43 static inline unsigned long get_plla_clk_rate(void)
44 {
45 	DECLARE_GLOBAL_DATA_PTR;
46 	return gd->arch.plla_rate_hz;
47 }
48 
49 static inline unsigned long get_pllb_clk_rate(void)
50 {
51 	DECLARE_GLOBAL_DATA_PTR;
52 	return gd->arch.pllb_rate_hz;
53 }
54 
55 static inline u32 get_pllb_init(void)
56 {
57 	DECLARE_GLOBAL_DATA_PTR;
58 	return gd->arch.at91_pllb_usb_init;
59 }
60 
61 #ifdef CPU_HAS_H32MXDIV
62 static inline unsigned int get_h32mxdiv(void)
63 {
64 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
65 
66 	return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
67 }
68 #else
69 static inline unsigned int get_h32mxdiv(void)
70 {
71 	return 0;
72 }
73 #endif
74 
75 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
76 {
77 	if (get_h32mxdiv())
78 		return get_mck_clk_rate() / 2;
79 	else
80 		return get_mck_clk_rate();
81 }
82 
83 static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
84 {
85 	if (get_h32mxdiv())
86 		return get_mck_clk_rate() / 2;
87 	else
88 		return get_mck_clk_rate();
89 }
90 
91 static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
92 {
93 	return get_mck_clk_rate();
94 }
95 
96 static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
97 {
98 	if (get_h32mxdiv())
99 		return get_mck_clk_rate() / 2;
100 	else
101 		return get_mck_clk_rate();
102 }
103 
104 static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
105 {
106 	if (get_h32mxdiv())
107 		return get_mck_clk_rate() / 2;
108 	else
109 		return get_mck_clk_rate();
110 }
111 
112 static inline unsigned long get_mci_clk_rate(void)
113 {
114 	if (get_h32mxdiv())
115 		return get_mck_clk_rate() / 2;
116 	else
117 		return get_mck_clk_rate();
118 }
119 
120 static inline unsigned long get_pit_clk_rate(void)
121 {
122 	if (get_h32mxdiv())
123 		return get_mck_clk_rate() / 2;
124 	else
125 		return get_mck_clk_rate();
126 }
127 
128 int at91_clock_init(unsigned long main_clock);
129 void at91_periph_clk_enable(int id);
130 void at91_periph_clk_disable(int id);
131 int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div);
132 u32 at91_get_periph_generated_clk(u32 id);
133 void at91_system_clk_enable(int sys_clk);
134 void at91_system_clk_disable(int sys_clk);
135 int at91_upll_clk_enable(void);
136 int at91_upll_clk_disable(void);
137 void at91_usb_clk_init(u32 value);
138 int at91_pllb_clk_enable(u32 pllbr);
139 int at91_pllb_clk_disable(void);
140 void at91_pllicpr_init(u32 icpr);
141 
142 #endif /* __ASM_ARM_ARCH_CLK_H__ */
143