1 /* 2 * Copyright (C) 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ATMEL_MPDDRC_H__ 9 #define __ATMEL_MPDDRC_H__ 10 11 struct atmel_mpddrc_config { 12 u32 mr; 13 u32 rtr; 14 u32 cr; 15 u32 tpr0; 16 u32 tpr1; 17 u32 tpr2; 18 u32 md; 19 }; 20 21 /* 22 * Only define the needed register in mpddr 23 * If other register needed, will add them later 24 */ 25 struct atmel_mpddr { 26 u32 mr; 27 u32 rtr; 28 u32 cr; 29 u32 tpr0; 30 u32 tpr1; 31 u32 tpr2; 32 u32 reserved[2]; 33 u32 md; 34 }; 35 36 37 int ddr2_init(const unsigned int base, 38 const unsigned int ram_address, 39 const struct atmel_mpddrc_config *mpddr_value); 40 41 /* Bit field in mode register */ 42 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 43 #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 44 #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 45 #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 46 #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 47 #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 48 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 49 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 50 51 /* Bit field in configuration register */ 52 #define ATMEL_MPDDRC_CR_NC_MASK 0x3 53 #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 54 #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 55 #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 56 #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 57 #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 58 #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 59 #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 60 #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 61 #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 62 #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 63 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 64 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 65 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 66 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 67 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 68 #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 69 #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 70 #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 71 #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 72 #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 73 #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 74 #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 75 #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 76 #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 77 #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 78 79 /* Bit field in timing parameter 0 register */ 80 #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 81 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 82 #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 83 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 84 #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 85 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 86 #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 87 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 88 #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 89 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 90 #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 91 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 92 #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 93 #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 94 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 95 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 96 #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 97 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 98 99 /* Bit field in timing parameter 1 register */ 100 #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 101 #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 102 #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 103 #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 104 #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 105 #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 106 #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 107 #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 108 109 /* Bit field in timing parameter 2 register */ 110 #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 111 #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 112 #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 113 #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 114 #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 115 #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 116 #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 117 #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 118 #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 119 #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 120 121 /* Bit field in Memory Device Register */ 122 #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 123 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 124 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 125 #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 126 #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 127 128 #endif 129