1 /* 2 * Copyright (C) 2013 Atmel Corporation 3 * Bo Shen <voice.shen@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ATMEL_MPDDRC_H__ 9 #define __ATMEL_MPDDRC_H__ 10 11 /* 12 * Only define the needed register in mpddr 13 * If other register needed, will add them later 14 */ 15 struct atmel_mpddr { 16 u32 mr; 17 u32 rtr; 18 u32 cr; 19 u32 tpr0; 20 u32 tpr1; 21 u32 tpr2; 22 u32 reserved[2]; 23 u32 md; 24 }; 25 26 27 int ddr2_init(const unsigned int base, 28 const unsigned int ram_address, 29 const struct atmel_mpddr *mpddr); 30 31 /* Bit field in mode register */ 32 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 33 #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 34 #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 35 #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 36 #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 37 #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 38 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 39 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 40 41 /* Bit field in configuration register */ 42 #define ATMEL_MPDDRC_CR_NC_MASK 0x3 43 #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 44 #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 45 #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 46 #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 47 #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 48 #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 49 #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 50 #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 51 #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 52 #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 53 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 54 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 55 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 56 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 57 #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 58 #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 59 #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 60 #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 61 #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 62 #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 63 #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 64 #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 65 #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 66 #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 67 #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 68 69 /* Bit field in timing parameter 0 register */ 70 #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 71 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 72 #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 73 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 74 #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 75 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 76 #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 77 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 78 #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 79 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 80 #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 81 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 82 #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 83 #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 84 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 85 #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 86 #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 87 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 88 89 /* Bit field in timing parameter 1 register */ 90 #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 91 #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 92 #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 93 #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 94 #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 95 #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 96 #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 97 #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 98 99 /* Bit field in timing parameter 2 register */ 100 #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 101 #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 102 #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 103 #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 104 #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 105 #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 106 #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 107 #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 108 #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 109 #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 110 111 /* Bit field in Memory Device Register */ 112 #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 113 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 114 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 115 #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 116 #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 117 118 #endif 119