1af930827SMasahiro Yamada /* 2af930827SMasahiro Yamada * Copyright (C) 2013 Atmel Corporation 3af930827SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 4af930827SMasahiro Yamada * 5af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6af930827SMasahiro Yamada */ 7af930827SMasahiro Yamada 8af930827SMasahiro Yamada #ifndef __ATMEL_MPDDRC_H__ 9af930827SMasahiro Yamada #define __ATMEL_MPDDRC_H__ 10af930827SMasahiro Yamada 11*7e8702a0SWenyou Yang struct atmel_mpddrc_config { 12*7e8702a0SWenyou Yang u32 mr; 13*7e8702a0SWenyou Yang u32 rtr; 14*7e8702a0SWenyou Yang u32 cr; 15*7e8702a0SWenyou Yang u32 tpr0; 16*7e8702a0SWenyou Yang u32 tpr1; 17*7e8702a0SWenyou Yang u32 tpr2; 18*7e8702a0SWenyou Yang u32 md; 19*7e8702a0SWenyou Yang }; 20*7e8702a0SWenyou Yang 21af930827SMasahiro Yamada /* 22af930827SMasahiro Yamada * Only define the needed register in mpddr 23af930827SMasahiro Yamada * If other register needed, will add them later 24af930827SMasahiro Yamada */ 25af930827SMasahiro Yamada struct atmel_mpddr { 26af930827SMasahiro Yamada u32 mr; 27af930827SMasahiro Yamada u32 rtr; 28af930827SMasahiro Yamada u32 cr; 29af930827SMasahiro Yamada u32 tpr0; 30af930827SMasahiro Yamada u32 tpr1; 31af930827SMasahiro Yamada u32 tpr2; 32af930827SMasahiro Yamada u32 reserved[2]; 33af930827SMasahiro Yamada u32 md; 34af930827SMasahiro Yamada }; 35af930827SMasahiro Yamada 360c01c3e8SErik van Luijk 370c01c3e8SErik van Luijk int ddr2_init(const unsigned int base, 380c01c3e8SErik van Luijk const unsigned int ram_address, 39*7e8702a0SWenyou Yang const struct atmel_mpddrc_config *mpddr_value); 40af930827SMasahiro Yamada 41af930827SMasahiro Yamada /* Bit field in mode register */ 42af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 43af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 44af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 45af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 46af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 47af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 48af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 49af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 50af930827SMasahiro Yamada 51af930827SMasahiro Yamada /* Bit field in configuration register */ 52af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_MASK 0x3 53af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 54af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 55af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 56af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 57af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 58af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 59af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 60af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 61af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 62af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 63af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 64af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 65af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 66af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 67af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 68af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 69af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 70af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 71af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 72af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 73af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 74af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 75af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 76af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 77af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 78af930827SMasahiro Yamada 79af930827SMasahiro Yamada /* Bit field in timing parameter 0 register */ 80af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 81af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 82af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 83af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 84af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 85af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 86af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 87af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 88af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 89af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 90af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 91af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 92af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 93af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 94af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 95af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 96af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 97af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 98af930827SMasahiro Yamada 99af930827SMasahiro Yamada /* Bit field in timing parameter 1 register */ 100af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 101af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 102af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 103af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 104af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 105af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 106af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 107af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 108af930827SMasahiro Yamada 109af930827SMasahiro Yamada /* Bit field in timing parameter 2 register */ 110af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 111af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 112af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 113af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 114af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 115af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 116af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 117af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 118af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 119af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 120af930827SMasahiro Yamada 121af930827SMasahiro Yamada /* Bit field in Memory Device Register */ 122af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 123af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 124af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 125af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 126af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 127af930827SMasahiro Yamada 128af930827SMasahiro Yamada #endif 129