1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * Copyright (C) 2013 Atmel Corporation 4af930827SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 5af930827SMasahiro Yamada * 6c2ad76c4SWenyou Yang * Copyright (C) 2015 Atmel Corporation 7c2ad76c4SWenyou Yang * Wenyou Yang <wenyou.yang@atmel.com> 8af930827SMasahiro Yamada */ 9af930827SMasahiro Yamada 10af930827SMasahiro Yamada #ifndef __ATMEL_MPDDRC_H__ 11af930827SMasahiro Yamada #define __ATMEL_MPDDRC_H__ 12af930827SMasahiro Yamada 137e8702a0SWenyou Yang struct atmel_mpddrc_config { 147e8702a0SWenyou Yang u32 mr; 157e8702a0SWenyou Yang u32 rtr; 167e8702a0SWenyou Yang u32 cr; 177e8702a0SWenyou Yang u32 tpr0; 187e8702a0SWenyou Yang u32 tpr1; 197e8702a0SWenyou Yang u32 tpr2; 207e8702a0SWenyou Yang u32 md; 217e8702a0SWenyou Yang }; 227e8702a0SWenyou Yang 23af930827SMasahiro Yamada /* 24af930827SMasahiro Yamada * Only define the needed register in mpddr 25af930827SMasahiro Yamada * If other register needed, will add them later 26af930827SMasahiro Yamada */ 27af930827SMasahiro Yamada struct atmel_mpddr { 28c2ad76c4SWenyou Yang u32 mr; /* 0x00: Mode Register */ 29c2ad76c4SWenyou Yang u32 rtr; /* 0x04: Refresh Timer Register */ 30c2ad76c4SWenyou Yang u32 cr; /* 0x08: Configuration Register */ 31c2ad76c4SWenyou Yang u32 tpr0; /* 0x0c: Timing Parameter 0 Register */ 32c2ad76c4SWenyou Yang u32 tpr1; /* 0x10: Timing Parameter 1 Register */ 33c2ad76c4SWenyou Yang u32 tpr2; /* 0x14: Timing Parameter 2 Register */ 34c2ad76c4SWenyou Yang u32 reserved; /* 0x18: Reserved */ 35c2ad76c4SWenyou Yang u32 lpr; /* 0x1c: Low-power Register */ 36c2ad76c4SWenyou Yang u32 md; /* 0x20: Memory Device Register */ 37c2ad76c4SWenyou Yang u32 reserved1; /* 0x24: Reserved */ 38c2ad76c4SWenyou Yang u32 lpddr23_lpr; /* 0x28: LPDDR2-LPDDR3 Low-power Register*/ 39c2ad76c4SWenyou Yang u32 cal_mr4; /* 0x2c: Calibration and MR4 Register */ 40c2ad76c4SWenyou Yang u32 tim_cal; /* 0x30: Timing Calibration Register */ 41c2ad76c4SWenyou Yang u32 io_calibr; /* 0x34: IO Calibration */ 42c2ad76c4SWenyou Yang u32 ocms; /* 0x38: OCMS Register */ 43c2ad76c4SWenyou Yang u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */ 44c2ad76c4SWenyou Yang u32 ocms_key2; /* 0x40: OCMS KEY2 Register */ 45c2ad76c4SWenyou Yang u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */ 46c2ad76c4SWenyou Yang u32 timeout; /* 0x48: Timeout Port 0/1/2/3 Register */ 47c2ad76c4SWenyou Yang u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */ 48c2ad76c4SWenyou Yang u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */ 49c2ad76c4SWenyou Yang u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */ 50c2ad76c4SWenyou Yang u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */ 51c2ad76c4SWenyou Yang u32 rd_data_path; /* 0x5c: Read Datapath Register */ 52c2ad76c4SWenyou Yang u32 reserved2[33]; 53c2ad76c4SWenyou Yang u32 wpmr; /* 0xe4: Write Protection Mode Register */ 54c2ad76c4SWenyou Yang u32 wpsr; /* 0xe8: Write Protection Status Register */ 55c2ad76c4SWenyou Yang u32 reserved3[4]; 56c2ad76c4SWenyou Yang u32 version; /* 0xfc: IP version */ 57af930827SMasahiro Yamada }; 58af930827SMasahiro Yamada 590c01c3e8SErik van Luijk 600c01c3e8SErik van Luijk int ddr2_init(const unsigned int base, 610c01c3e8SErik van Luijk const unsigned int ram_address, 627e8702a0SWenyou Yang const struct atmel_mpddrc_config *mpddr_value); 63af930827SMasahiro Yamada 64c2ad76c4SWenyou Yang int ddr3_init(const unsigned int base, 65c2ad76c4SWenyou Yang const unsigned int ram_address, 66c2ad76c4SWenyou Yang const struct atmel_mpddrc_config *mpddr_value); 67c2ad76c4SWenyou Yang 68af930827SMasahiro Yamada /* Bit field in mode register */ 69af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 70af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1 71af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD 0x2 72af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_LMR_CMD 0x3 73af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_RFSH_CMD 0x4 74af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 75af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 76af930827SMasahiro Yamada #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 77af930827SMasahiro Yamada 78af930827SMasahiro Yamada /* Bit field in configuration register */ 79af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_MASK 0x3 80af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_9 0x0 81af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_10 0x1 82af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_11 0x2 83af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NC_COL_12 0x3 84af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_MASK (0x3 << 2) 85af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_11 (0x0 << 2) 86af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_12 (0x1 << 2) 87af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_13 (0x2 << 2) 88af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NR_ROW_14 (0x3 << 2) 89af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_MASK (0x7 << 4) 90af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS2 (0x2 << 4) 91af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS3 (0x3 << 4) 92af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS4 (0x4 << 4) 93af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS5 (0x5 << 4) 94af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_CAS_DDR_CAS6 (0x6 << 4) 95af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED (0x1 << 7) 96af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) 97af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) 98b5c13dacSWenyou Yang #define ATMEL_MPDDRC_CR_ZQ_INIT (0x0 << 10) 99b5c13dacSWenyou Yang #define ATMEL_MPDDRC_CR_ZQ_LONG (0x1 << 10) 100b5c13dacSWenyou Yang #define ATMEL_MPDDRC_CR_ZQ_SHORT (0x2 << 10) 101b5c13dacSWenyou Yang #define ATMEL_MPDDRC_CR_ZQ_RESET (0x3 << 10) 102af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) 103af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) 104af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) 105af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) 106af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) 107af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED (0x1 << 22) 108af930827SMasahiro Yamada #define ATMEL_MPDDRC_CR_UNAL_SUPPORTED (0x1 << 23) 109af930827SMasahiro Yamada 110af930827SMasahiro Yamada /* Bit field in timing parameter 0 register */ 111af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRAS_OFFSET 0 112af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf 113af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRCD_OFFSET 4 114af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf 115af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWR_OFFSET 8 116af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf 117af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRC_OFFSET 12 118af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf 119af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRP_OFFSET 16 120af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf 121af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRRD_OFFSET 20 122af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf 123af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWTR_OFFSET 24 124af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TWTR_MASK 0x7 125af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET 27 126af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK 0x1 127af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TMRD_OFFSET 28 128af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf 129af930827SMasahiro Yamada 130af930827SMasahiro Yamada /* Bit field in timing parameter 1 register */ 131af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TRFC_OFFSET 0 132af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TRFC_MASK 0x7f 133af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET 8 134af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSNR_MASK 0xff 135af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET 16 136af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXSRD_MASK 0xff 137af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXP_OFFSET 24 138af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf 139af930827SMasahiro Yamada 140af930827SMasahiro Yamada /* Bit field in timing parameter 2 register */ 141af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARD_OFFSET 0 142af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf 143af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET 4 144af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf 145af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRPA_OFFSET 8 146af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRPA_MASK 0xf 147af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRTP_OFFSET 12 148af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TRTP_MASK 0x7 149af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TFAW_OFFSET 16 150af930827SMasahiro Yamada #define ATMEL_MPDDRC_TPR2_TFAW_MASK 0xf 151af930827SMasahiro Yamada 152af930827SMasahiro Yamada /* Bit field in Memory Device Register */ 15320e00c13SHeiko Schocher #define ATMEL_MPDDRC_MD_SDR_SDRAM 0x0 15420e00c13SHeiko Schocher #define ATMEL_MPDDRC_MD_LP_SDR_SDRAM 0x1 15520e00c13SHeiko Schocher #define ATMEL_MPDDRC_MD_DDR_SDRAM 0x2 156af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_LPDDR_SDRAM 0x3 157c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 158c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 159af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 160af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) 161af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) 162af930827SMasahiro Yamada #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) 163af930827SMasahiro Yamada 164c2ad76c4SWenyou Yang /* Bit field in I/O Calibration Register */ 165c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_RDIV 0x7 166c2ad76c4SWenyou Yang 167c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1 168c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2 169c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3 170c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4 171c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6 172c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7 173c2ad76c4SWenyou Yang 174c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2 175c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3 176c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4 177c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6 178c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_105 0x7 179c2ad76c4SWenyou Yang 180c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 181c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 182c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 183c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 184c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 185c2ad76c4SWenyou Yang 186c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2 187c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3 188c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55 0x4 189c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6 190c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7 191c2ad76c4SWenyou Yang 1920d00f9b6SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8) 193c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8) 194c2ad76c4SWenyou Yang 1950d00f9b6SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16) 1960d00f9b6SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16) 1970d00f9b6SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20) 1980d00f9b6SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20) 1990d00f9b6SWenyou Yang 200c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4) 201c2ad76c4SWenyou Yang 202c2ad76c4SWenyou Yang /* Bit field in Read Data Path Register */ 203c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_SAMPLING 0x3 204c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_RD_DATA_PATH_NO_SHIFT 0x0 205c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE 0x1 206c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 207c2ad76c4SWenyou Yang #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3 208c2ad76c4SWenyou Yang 209af930827SMasahiro Yamada #endif 210