1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * Chip-specific header file for the AT91SAM9x5 family 4af930827SMasahiro Yamada * 5af930827SMasahiro Yamada * Copyright (C) 2012-2013 Atmel Corporation. 6af930827SMasahiro Yamada * 7af930827SMasahiro Yamada * Definitions for the SoC: 8af930827SMasahiro Yamada * AT91SAM9x5 & AT91SAM9N12 9af930827SMasahiro Yamada */ 10af930827SMasahiro Yamada 11af930827SMasahiro Yamada #ifndef __AT91SAM9X5_H__ 12af930827SMasahiro Yamada #define __AT91SAM9X5_H__ 13af930827SMasahiro Yamada 14af930827SMasahiro Yamada /* 15af930827SMasahiro Yamada * Peripheral identifiers/interrupts. 16af930827SMasahiro Yamada */ 17af930827SMasahiro Yamada #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 18af930827SMasahiro Yamada #define ATMEL_ID_SYS 1 /* System Controller Interrupt */ 19af930827SMasahiro Yamada #define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */ 20af930827SMasahiro Yamada #define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */ 21af930827SMasahiro Yamada #define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */ 22af930827SMasahiro Yamada #define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */ 23af930827SMasahiro Yamada #define ATMEL_ID_USART0 5 /* USART 0 */ 24af930827SMasahiro Yamada #define ATMEL_ID_USART1 6 /* USART 1 */ 25af930827SMasahiro Yamada #define ATMEL_ID_USART2 7 /* USART 2 */ 26af930827SMasahiro Yamada #define ATMEL_ID_USART3 8 /* USART 3 */ 27af930827SMasahiro Yamada #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */ 28af930827SMasahiro Yamada #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */ 29af930827SMasahiro Yamada #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */ 30af930827SMasahiro Yamada #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */ 31af930827SMasahiro Yamada #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */ 32af930827SMasahiro Yamada #define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */ 33af930827SMasahiro Yamada #define ATMEL_ID_UART0 15 /* UART 0 */ 34af930827SMasahiro Yamada #define ATMEL_ID_UART1 16 /* UART 1 */ 35af930827SMasahiro Yamada #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ 36af930827SMasahiro Yamada #define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ 37af930827SMasahiro Yamada #define ATMEL_ID_ADC 19 /* ADC Controller */ 38af930827SMasahiro Yamada #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */ 39af930827SMasahiro Yamada #define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */ 40af930827SMasahiro Yamada #define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ 41af930827SMasahiro Yamada #define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ 42af930827SMasahiro Yamada #define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */ 43af930827SMasahiro Yamada #define ATMEL_ID_LCDC 25 /* LCD Controller */ 44af930827SMasahiro Yamada #define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */ 45af930827SMasahiro Yamada #define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */ 46af930827SMasahiro Yamada #define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ 47af930827SMasahiro Yamada #define ATMEL_ID_TRNG 30 /* True Random Number Generator */ 48af930827SMasahiro Yamada #define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ 49af930827SMasahiro Yamada 50af930827SMasahiro Yamada /* 51af930827SMasahiro Yamada * User Peripheral physical base addresses. 52af930827SMasahiro Yamada */ 53af930827SMasahiro Yamada #define ATMEL_BASE_SPI0 0xf0000000 54af930827SMasahiro Yamada #define ATMEL_BASE_SPI1 0xf0004000 55af930827SMasahiro Yamada #define ATMEL_BASE_HSMCI0 0xf0008000 56af930827SMasahiro Yamada #define ATMEL_BASE_HSMCI1 0xf000c000 57af930827SMasahiro Yamada #define ATMEL_BASE_SSC 0xf0010000 58af930827SMasahiro Yamada #define ATMEL_BASE_CAN0 0xf8000000 59af930827SMasahiro Yamada #define ATMEL_BASE_CAN1 0xf8004000 60af930827SMasahiro Yamada #define ATMEL_BASE_TC0 0xf8008000 61af930827SMasahiro Yamada #define ATMEL_BASE_TC1 0xf8008040 62af930827SMasahiro Yamada #define ATMEL_BASE_TC2 0xf8008080 63af930827SMasahiro Yamada #define ATMEL_BASE_TC3 0xf800c000 64af930827SMasahiro Yamada #define ATMEL_BASE_TC4 0xf800c040 65af930827SMasahiro Yamada #define ATMEL_BASE_TC5 0xf800c080 66af930827SMasahiro Yamada #define ATMEL_BASE_TWI0 0xf8010000 67af930827SMasahiro Yamada #define ATMEL_BASE_TWI1 0xf8014000 68af930827SMasahiro Yamada #define ATMEL_BASE_TWI2 0xf8018000 69af930827SMasahiro Yamada #define ATMEL_BASE_USART0 0xf801c000 70af930827SMasahiro Yamada #define ATMEL_BASE_USART1 0xf8020000 71af930827SMasahiro Yamada #define ATMEL_BASE_USART2 0xf8024000 72af930827SMasahiro Yamada #define ATMEL_BASE_USART3 0xf8028000 73af930827SMasahiro Yamada #define ATMEL_BASE_EMAC0 0xf802c000 74af930827SMasahiro Yamada #define ATMEL_BASE_EMAC1 0xf8030000 75af930827SMasahiro Yamada #define ATMEL_BASE_PWM 0xf8034000 76af930827SMasahiro Yamada #define ATMEL_BASE_LCDC 0xf8038000 77af930827SMasahiro Yamada #define ATMEL_BASE_UDPHS 0xf803c000 78af930827SMasahiro Yamada #define ATMEL_BASE_UART0 0xf8040000 79af930827SMasahiro Yamada #define ATMEL_BASE_UART1 0xf8044000 80af930827SMasahiro Yamada #define ATMEL_BASE_ISI 0xf8048000 81af930827SMasahiro Yamada #define ATMEL_BASE_ADC 0xf804c000 82af930827SMasahiro Yamada #define ATMEL_BASE_SYS 0xffffc000 83af930827SMasahiro Yamada 84af930827SMasahiro Yamada /* 85af930827SMasahiro Yamada * System Peripherals 86af930827SMasahiro Yamada */ 87af930827SMasahiro Yamada #define ATMEL_BASE_FUSE 0xffffdc00 88af930827SMasahiro Yamada #define ATMEL_BASE_MATRIX 0xffffde00 89af930827SMasahiro Yamada #define ATMEL_BASE_PMECC 0xffffe000 90af930827SMasahiro Yamada #define ATMEL_BASE_PMERRLOC 0xffffe600 91af930827SMasahiro Yamada #define ATMEL_BASE_DDRSDRC 0xffffe800 92af930827SMasahiro Yamada #define ATMEL_BASE_SMC 0xffffea00 93af930827SMasahiro Yamada #define ATMEL_BASE_DMAC0 0xffffec00 94af930827SMasahiro Yamada #define ATMEL_BASE_DMAC1 0xffffee00 95af930827SMasahiro Yamada #define ATMEL_BASE_AIC 0xfffff000 96af930827SMasahiro Yamada #define ATMEL_BASE_DBGU 0xfffff200 97af930827SMasahiro Yamada #define ATMEL_BASE_PIOA 0xfffff400 98af930827SMasahiro Yamada #define ATMEL_BASE_PIOB 0xfffff600 99af930827SMasahiro Yamada #define ATMEL_BASE_PIOC 0xfffff800 100af930827SMasahiro Yamada #define ATMEL_BASE_PIOD 0xfffffa00 101af930827SMasahiro Yamada #define ATMEL_BASE_PMC 0xfffffc00 102af930827SMasahiro Yamada #define ATMEL_BASE_RSTC 0xfffffe00 103af930827SMasahiro Yamada #define ATMEL_BASE_SHDWC 0xfffffe10 104af930827SMasahiro Yamada #define ATMEL_BASE_PIT 0xfffffe30 105af930827SMasahiro Yamada #define ATMEL_BASE_WDT 0xfffffe40 106af930827SMasahiro Yamada #define ATMEL_BASE_GPBR 0xfffffe60 107af930827SMasahiro Yamada #define ATMEL_BASE_RTC 0xfffffeb0 108af930827SMasahiro Yamada 109af930827SMasahiro Yamada /* 110af930827SMasahiro Yamada * Internal Memory. 111af930827SMasahiro Yamada */ 112af930827SMasahiro Yamada #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ 113af930827SMasahiro Yamada #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ 114af930827SMasahiro Yamada 115af930827SMasahiro Yamada #ifdef CONFIG_AT91SAM9N12 116af930827SMasahiro Yamada #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */ 117af930827SMasahiro Yamada #else /* AT91SAM9X5 */ 118af930827SMasahiro Yamada #define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */ 119af930827SMasahiro Yamada #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ 120af930827SMasahiro Yamada #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ 121af930827SMasahiro Yamada #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ 122af930827SMasahiro Yamada #endif 123af930827SMasahiro Yamada 124d85e8914SBo Shen /* 125d85e8914SBo Shen * External memory 126d85e8914SBo Shen */ 127d85e8914SBo Shen #define ATMEL_BASE_CS0 0x10000000 128d85e8914SBo Shen #define ATMEL_BASE_CS1 0x20000000 129d85e8914SBo Shen #define ATMEL_BASE_CS2 0x30000000 130d85e8914SBo Shen #define ATMEL_BASE_CS3 0x40000000 131d85e8914SBo Shen #define ATMEL_BASE_CS4 0x50000000 132d85e8914SBo Shen #define ATMEL_BASE_CS5 0x60000000 133d85e8914SBo Shen 134af930827SMasahiro Yamada /* 9x5 series chip id definitions */ 135af930827SMasahiro Yamada #define ARCH_ID_AT91SAM9X5 0x819a05a0 136af930827SMasahiro Yamada #define ARCH_ID_VERSION_MASK 0x1f 137af930827SMasahiro Yamada #define ARCH_EXID_AT91SAM9G15 0x00000000 138af930827SMasahiro Yamada #define ARCH_EXID_AT91SAM9G35 0x00000001 139af930827SMasahiro Yamada #define ARCH_EXID_AT91SAM9X35 0x00000002 140af930827SMasahiro Yamada #define ARCH_EXID_AT91SAM9G25 0x00000003 141af930827SMasahiro Yamada #define ARCH_EXID_AT91SAM9X25 0x00000004 142af930827SMasahiro Yamada 143af930827SMasahiro Yamada #define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5) 144af930827SMasahiro Yamada #define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ 145af930827SMasahiro Yamada (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15)) 146af930827SMasahiro Yamada #define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ 147af930827SMasahiro Yamada (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25)) 148af930827SMasahiro Yamada #define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ 149af930827SMasahiro Yamada (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35)) 150af930827SMasahiro Yamada #define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ 151af930827SMasahiro Yamada (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25)) 152af930827SMasahiro Yamada #define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ 153af930827SMasahiro Yamada (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35)) 154af930827SMasahiro Yamada 155af930827SMasahiro Yamada /* 156af930827SMasahiro Yamada * Cpu Name 157af930827SMasahiro Yamada */ 158af930827SMasahiro Yamada #ifdef CONFIG_AT91SAM9N12 159af930827SMasahiro Yamada #define ATMEL_CPU_NAME "AT91SAM9N12" 160af930827SMasahiro Yamada #else /* AT91SAM9X5 */ 161af930827SMasahiro Yamada #define ATMEL_CPU_NAME get_cpu_name() 162af930827SMasahiro Yamada #endif 163af930827SMasahiro Yamada 164a02c8a31SBo Shen /* Timer */ 165a02c8a31SBo Shen #define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c 166a02c8a31SBo Shen 167af930827SMasahiro Yamada /* 168af930827SMasahiro Yamada * Other misc defines 169af930827SMasahiro Yamada */ 170af930827SMasahiro Yamada #define ATMEL_PIO_PORTS 4 171af930827SMasahiro Yamada #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 172af930827SMasahiro Yamada #define ATMEL_ID_UHP ATMEL_ID_UHPHS 173af930827SMasahiro Yamada 174af930827SMasahiro Yamada /* 175af930827SMasahiro Yamada * PMECC table in ROM 176af930827SMasahiro Yamada */ 177af930827SMasahiro Yamada #define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 178af930827SMasahiro Yamada #define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 179af930827SMasahiro Yamada 180af930827SMasahiro Yamada /* 181af930827SMasahiro Yamada * at91sam9x5 specific prototypes 182af930827SMasahiro Yamada */ 183af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 184af930827SMasahiro Yamada unsigned int get_chip_id(void); 185af930827SMasahiro Yamada unsigned int get_extension_chip_id(void); 186af930827SMasahiro Yamada unsigned int has_emac1(void); 187af930827SMasahiro Yamada unsigned int has_emac0(void); 188af930827SMasahiro Yamada unsigned int has_lcdc(void); 189af930827SMasahiro Yamada char *get_cpu_name(void); 190af930827SMasahiro Yamada #endif 191af930827SMasahiro Yamada 192af930827SMasahiro Yamada #endif 193