1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Matrix-centric header file for the AT91SAM9M1x family 4 * 5 * Copyright (C) 2008 Atmel Corporation. 6 * 7 * Memory Controllers (MATRIX, EBI) - System peripherals registers. 8 * Based on AT91SAM9G45 preliminary datasheet. 9 */ 10 11 #ifndef AT91SAM9G45_MATRIX_H 12 #define AT91SAM9G45_MATRIX_H 13 14 #ifndef __ASSEMBLY__ 15 16 struct at91_matrix { 17 u32 mcfg[16]; 18 u32 scfg[16]; 19 u32 pras[16][2]; 20 u32 mrcr; /* 0x100 Master Remap Control */ 21 u32 filler[3]; 22 u32 tcmr; 23 u32 filler2; 24 u32 ddrmpr; 25 u32 filler3[3]; 26 u32 ebicsa; 27 u32 filler4[47]; 28 u32 wpmr; 29 u32 wpsr; 30 }; 31 32 #endif /* __ASSEMBLY__ */ 33 34 #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 35 #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 36 #define AT91_MATRIX_ULBT_FOUR (2 << 0) 37 #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 38 #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 39 #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 40 #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 41 #define AT91_MATRIX_ULBT_128 (7 << 0) 42 43 #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44 #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 45 #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 46 #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 47 48 #define AT91_MATRIX_M0PR_SHIFT 0 49 #define AT91_MATRIX_M1PR_SHIFT 4 50 #define AT91_MATRIX_M2PR_SHIFT 8 51 #define AT91_MATRIX_M3PR_SHIFT 12 52 #define AT91_MATRIX_M4PR_SHIFT 16 53 #define AT91_MATRIX_M5PR_SHIFT 20 54 #define AT91_MATRIX_M6PR_SHIFT 24 55 #define AT91_MATRIX_M7PR_SHIFT 28 56 57 #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ 58 #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ 59 #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ 60 #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ 61 62 #define AT91_MATRIX_RCB0 (1 << 0) 63 #define AT91_MATRIX_RCB1 (1 << 1) 64 #define AT91_MATRIX_RCB2 (1 << 2) 65 #define AT91_MATRIX_RCB3 (1 << 3) 66 #define AT91_MATRIX_RCB4 (1 << 4) 67 #define AT91_MATRIX_RCB5 (1 << 5) 68 #define AT91_MATRIX_RCB6 (1 << 6) 69 #define AT91_MATRIX_RCB7 (1 << 7) 70 #define AT91_MATRIX_RCB8 (1 << 8) 71 #define AT91_MATRIX_RCB9 (1 << 9) 72 #define AT91_MATRIX_RCB10 (1 << 10) 73 74 #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 75 #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 76 #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 77 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 78 #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) 79 #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) 80 #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) 81 #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) 82 #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 83 #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 84 #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 85 #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 86 #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 87 #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 88 #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 89 #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 90 91 #endif 92