1 /*
2  * Matrix-centric header file for the AT91SAM9M1x family
3  *
4  *  Copyright (C) 2008 Atmel Corporation.
5  *
6  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
7  * Based on AT91SAM9G45 preliminary datasheet.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef AT91SAM9G45_MATRIX_H
13 #define AT91SAM9G45_MATRIX_H
14 
15 #ifndef __ASSEMBLY__
16 
17 struct at91_matrix {
18 	u32	mcfg[16];
19 	u32	scfg[16];
20 	u32	pras[16][2];
21 	u32	mrcr;           /* 0x100 Master Remap Control */
22 	u32	filler[3];
23 	u32	tcmr;
24 	u32	filler2;
25 	u32	ddrmpr;
26 	u32	filler3[3];
27 	u32	ebicsa;
28 	u32	filler4[47];
29 	u32	wpmr;
30 	u32	wpsr;
31 };
32 
33 #endif /* __ASSEMBLY__ */
34 
35 #define	AT91_MATRIX_ULBT_INFINITE	(0 << 0)
36 #define	AT91_MATRIX_ULBT_SINGLE		(1 << 0)
37 #define	AT91_MATRIX_ULBT_FOUR		(2 << 0)
38 #define	AT91_MATRIX_ULBT_EIGHT		(3 << 0)
39 #define	AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
40 #define	AT91_MATRIX_ULBT_THIRTYTWO	(5 << 0)
41 #define	AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
42 #define	AT91_MATRIX_ULBT_128		(7 << 0)
43 
44 #define	AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
45 #define	AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
46 #define	AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
47 #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
48 
49 #define AT91_MATRIX_M0PR_SHIFT          0
50 #define AT91_MATRIX_M1PR_SHIFT          4
51 #define AT91_MATRIX_M2PR_SHIFT          8
52 #define AT91_MATRIX_M3PR_SHIFT          12
53 #define AT91_MATRIX_M4PR_SHIFT          16
54 #define AT91_MATRIX_M5PR_SHIFT          20
55 #define AT91_MATRIX_M6PR_SHIFT          24
56 #define AT91_MATRIX_M7PR_SHIFT          28
57 
58 #define AT91_MATRIX_M8PR_SHIFT          0  /* register B */
59 #define AT91_MATRIX_M9PR_SHIFT          4  /* register B */
60 #define AT91_MATRIX_M10PR_SHIFT         8  /* register B */
61 #define AT91_MATRIX_M11PR_SHIFT         12 /* register B */
62 
63 #define AT91_MATRIX_RCB0                (1 << 0)
64 #define AT91_MATRIX_RCB1                (1 << 1)
65 #define AT91_MATRIX_RCB2                (1 << 2)
66 #define AT91_MATRIX_RCB3                (1 << 3)
67 #define AT91_MATRIX_RCB4                (1 << 4)
68 #define AT91_MATRIX_RCB5                (1 << 5)
69 #define AT91_MATRIX_RCB6                (1 << 6)
70 #define AT91_MATRIX_RCB7                (1 << 7)
71 #define AT91_MATRIX_RCB8                (1 << 8)
72 #define AT91_MATRIX_RCB9                (1 << 9)
73 #define AT91_MATRIX_RCB10               (1 << 10)
74 
75 #define AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
76 #define AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
77 #define AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
78 #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
79 #define AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
80 #define AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
81 #define AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
82 #define AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
83 #define AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
84 #define AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
85 #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
86 #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
87 #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
88 #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
89 #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
90 #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
91 
92 #endif
93