1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * Matrix-centric header file for the AT91SAM9M1x family 4af930827SMasahiro Yamada * 5af930827SMasahiro Yamada * Copyright (C) 2008 Atmel Corporation. 6af930827SMasahiro Yamada * 7af930827SMasahiro Yamada * Memory Controllers (MATRIX, EBI) - System peripherals registers. 8af930827SMasahiro Yamada * Based on AT91SAM9G45 preliminary datasheet. 9af930827SMasahiro Yamada */ 10af930827SMasahiro Yamada 11af930827SMasahiro Yamada #ifndef AT91SAM9G45_MATRIX_H 12af930827SMasahiro Yamada #define AT91SAM9G45_MATRIX_H 13af930827SMasahiro Yamada 14af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 15af930827SMasahiro Yamada 16af930827SMasahiro Yamada struct at91_matrix { 17af930827SMasahiro Yamada u32 mcfg[16]; 18af930827SMasahiro Yamada u32 scfg[16]; 19af930827SMasahiro Yamada u32 pras[16][2]; 20af930827SMasahiro Yamada u32 mrcr; /* 0x100 Master Remap Control */ 21af930827SMasahiro Yamada u32 filler[3]; 22af930827SMasahiro Yamada u32 tcmr; 23af930827SMasahiro Yamada u32 filler2; 24af930827SMasahiro Yamada u32 ddrmpr; 25af930827SMasahiro Yamada u32 filler3[3]; 26af930827SMasahiro Yamada u32 ebicsa; 27af930827SMasahiro Yamada u32 filler4[47]; 28af930827SMasahiro Yamada u32 wpmr; 29af930827SMasahiro Yamada u32 wpsr; 30af930827SMasahiro Yamada }; 31af930827SMasahiro Yamada 32af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 33af930827SMasahiro Yamada 34af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 35af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 36af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_FOUR (2 << 0) 37af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 38af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 39af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) 40af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 41af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_128 (7 << 0) 42af930827SMasahiro Yamada 43af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 45af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 46af930827SMasahiro Yamada #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 47af930827SMasahiro Yamada 48af930827SMasahiro Yamada #define AT91_MATRIX_M0PR_SHIFT 0 49af930827SMasahiro Yamada #define AT91_MATRIX_M1PR_SHIFT 4 50af930827SMasahiro Yamada #define AT91_MATRIX_M2PR_SHIFT 8 51af930827SMasahiro Yamada #define AT91_MATRIX_M3PR_SHIFT 12 52af930827SMasahiro Yamada #define AT91_MATRIX_M4PR_SHIFT 16 53af930827SMasahiro Yamada #define AT91_MATRIX_M5PR_SHIFT 20 54af930827SMasahiro Yamada #define AT91_MATRIX_M6PR_SHIFT 24 55af930827SMasahiro Yamada #define AT91_MATRIX_M7PR_SHIFT 28 56af930827SMasahiro Yamada 57af930827SMasahiro Yamada #define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ 58af930827SMasahiro Yamada #define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ 59af930827SMasahiro Yamada #define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ 60af930827SMasahiro Yamada #define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ 61af930827SMasahiro Yamada 62af930827SMasahiro Yamada #define AT91_MATRIX_RCB0 (1 << 0) 63af930827SMasahiro Yamada #define AT91_MATRIX_RCB1 (1 << 1) 64af930827SMasahiro Yamada #define AT91_MATRIX_RCB2 (1 << 2) 65af930827SMasahiro Yamada #define AT91_MATRIX_RCB3 (1 << 3) 66af930827SMasahiro Yamada #define AT91_MATRIX_RCB4 (1 << 4) 67af930827SMasahiro Yamada #define AT91_MATRIX_RCB5 (1 << 5) 68af930827SMasahiro Yamada #define AT91_MATRIX_RCB6 (1 << 6) 69af930827SMasahiro Yamada #define AT91_MATRIX_RCB7 (1 << 7) 70af930827SMasahiro Yamada #define AT91_MATRIX_RCB8 (1 << 8) 71af930827SMasahiro Yamada #define AT91_MATRIX_RCB9 (1 << 9) 72af930827SMasahiro Yamada #define AT91_MATRIX_RCB10 (1 << 10) 73af930827SMasahiro Yamada 74af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 75af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 76af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) 77af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 78af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) 79af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) 80af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) 81af930827SMasahiro Yamada #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) 82af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) 83af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) 84af930827SMasahiro Yamada #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) 85af930827SMasahiro Yamada #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) 86af930827SMasahiro Yamada #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) 87af930827SMasahiro Yamada #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) 88af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 89af930827SMasahiro Yamada #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 90af930827SMasahiro Yamada 91af930827SMasahiro Yamada #endif 92