1 /*
2  * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
3  *
4  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5  * Copyright (C) 2007 Andrew Victor
6  * Copyright (C) 2007 Atmel Corporation.
7  *
8  * SDRAM Controllers (SDRAMC) - System peripherals registers.
9  * Based on AT91SAM9261 datasheet revision D.
10  *
11  * SPDX-License-Identifier:	GPL-2.0+
12  */
13 
14 #ifndef AT91SAM9_SDRAMC_H
15 #define AT91SAM9_SDRAMC_H
16 
17 #ifdef __ASSEMBLY__
18 
19 #ifndef ATMEL_BASE_SDRAMC
20 #define ATMEL_BASE_SDRAMC	ATMEL_BASE_SDRAMC0
21 #endif
22 
23 #define AT91_ASM_SDRAMC_MR	ATMEL_BASE_SDRAMC
24 #define AT91_ASM_SDRAMC_TR	(ATMEL_BASE_SDRAMC + 0x04)
25 #define AT91_ASM_SDRAMC_CR	(ATMEL_BASE_SDRAMC + 0x08)
26 #define AT91_ASM_SDRAMC_MDR	(ATMEL_BASE_SDRAMC + 0x24)
27 
28 #else
29 struct sdramc_reg {
30 	u32	mr;
31 	u32	tr;
32 	u32	cr;
33 	u32	lpr;
34 	u32	ier;
35 	u32	idr;
36 	u32	imr;
37 	u32	isr;
38 	u32	mdr;
39 };
40 
41 int sdramc_initialize(unsigned int sdram_address,
42 		      const struct sdramc_reg *p);
43 #endif
44 
45 /* SDRAM Controller (SDRAMC) registers */
46 #define AT91_SDRAMC_MR		(ATMEL_BASE_SDRAMC + 0x00)	/* SDRAM Controller Mode Register */
47 #define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
48 #define			AT91_SDRAMC_MODE_NORMAL		0
49 #define			AT91_SDRAMC_MODE_NOP		1
50 #define			AT91_SDRAMC_MODE_PRECHARGE	2
51 #define			AT91_SDRAMC_MODE_LMR		3
52 #define			AT91_SDRAMC_MODE_REFRESH	4
53 #define			AT91_SDRAMC_MODE_EXT_LMR	5
54 #define			AT91_SDRAMC_MODE_DEEP		6
55 
56 #define AT91_SDRAMC_TR		(ATMEL_BASE_SDRAMC + 0x04)	/* SDRAM Controller Refresh Timer Register */
57 #define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */
58 
59 #define AT91_SDRAMC_CR		(ATMEL_BASE_SDRAMC + 0x08)	/* SDRAM Controller Configuration Register */
60 #define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
61 #define			AT91_SDRAMC_NC_8	(0 << 0)
62 #define			AT91_SDRAMC_NC_9	(1 << 0)
63 #define			AT91_SDRAMC_NC_10	(2 << 0)
64 #define			AT91_SDRAMC_NC_11	(3 << 0)
65 #define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
66 #define			AT91_SDRAMC_NR_11	(0 << 2)
67 #define			AT91_SDRAMC_NR_12	(1 << 2)
68 #define			AT91_SDRAMC_NR_13	(2 << 2)
69 #define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
70 #define			AT91_SDRAMC_NB_2	(0 << 4)
71 #define			AT91_SDRAMC_NB_4	(1 << 4)
72 #define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
73 #define			AT91_SDRAMC_CAS_1	(1 << 5)
74 #define			AT91_SDRAMC_CAS_2	(2 << 5)
75 #define			AT91_SDRAMC_CAS_3	(3 << 5)
76 #define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
77 #define			AT91_SDRAMC_DBW_32	(0 << 7)
78 #define			AT91_SDRAMC_DBW_16	(1 << 7)
79 #define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
80 #define		AT91_SDRAMC_TWR_VAL(x)	(x << 8)
81 #define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
82 #define			AT91_SDRAMC_TRC_VAL(x)	(x << 12)
83 #define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
84 #define		AT91_SDRAMC_TRP_VAL(x)	(x << 16)
85 #define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
86 #define			AT91_SDRAMC_TRCD_VAL(x)	(x << 20)
87 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
88 #define		AT91_SDRAMC_TRAS_VAL(x)	(x << 24)
89 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
90 #define		AT91_SDRAMC_TXSR_VAL(x)	(x << 28)
91 
92 #define AT91_SDRAMC_LPR		(ATMEL_BASE_SDRAMC + 0x10)	/* SDRAM Controller Low Power Register */
93 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
94 #define			AT91_SDRAMC_LPCB_DISABLE		0
95 #define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
96 #define			AT91_SDRAMC_LPCB_POWER_DOWN		2
97 #define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
98 #define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
99 #define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
100 #define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
101 #define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
102 #define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
103 #define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
104 #define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)
105 
106 #define AT91_SDRAMC_IER		(ATMEL_BASE_SDRAMC + 0x14)	/* SDRAM Controller Interrupt Enable Register */
107 #define AT91_SDRAMC_IDR		(ATMEL_BASE_SDRAMC + 0x18)	/* SDRAM Controller Interrupt Disable Register */
108 #define AT91_SDRAMC_IMR		(ATMEL_BASE_SDRAMC + 0x1C)	/* SDRAM Controller Interrupt Mask Register */
109 #define AT91_SDRAMC_ISR		(ATMEL_BASE_SDRAMC + 0x20)	/* SDRAM Controller Interrupt Status Register */
110 #define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */
111 
112 #define AT91_SDRAMC_MDR		(ATMEL_BASE_SDRAMC + 0x24)	/* SDRAM Memory Device Register */
113 #define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
114 #define			AT91_SDRAMC_MD_SDRAM		0
115 #define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1
116 
117 #endif
118