1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] 4af930827SMasahiro Yamada * 5af930827SMasahiro Yamada * Copyright (C) 2006 Atmel Corporation. 6af930827SMasahiro Yamada * 7af930827SMasahiro Yamada * Memory Controllers (MATRIX, EBI) - System peripherals registers. 8af930827SMasahiro Yamada * Based on AT91SAM9263 datasheet revision B (Preliminary). 9af930827SMasahiro Yamada */ 10af930827SMasahiro Yamada 11af930827SMasahiro Yamada #ifndef AT91SAM9263_MATRIX_H 12af930827SMasahiro Yamada #define AT91SAM9263_MATRIX_H 13af930827SMasahiro Yamada 14af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 15af930827SMasahiro Yamada 16af930827SMasahiro Yamada /* 17af930827SMasahiro Yamada * This struct defines access to the matrix' maximum of 18af930827SMasahiro Yamada * 16 masters and 16 slaves. 19af930827SMasahiro Yamada * Note: not all masters/slaves are available 20af930827SMasahiro Yamada */ 21af930827SMasahiro Yamada struct at91_matrix { 22af930827SMasahiro Yamada u32 mcfg[16]; /* Master Configuration Registers */ 23af930827SMasahiro Yamada u32 scfg[16]; /* Slave Configuration Registers */ 24af930827SMasahiro Yamada u32 pras[16][2]; /* Priority Assignment Slave Registers */ 25af930827SMasahiro Yamada u32 mrcr; /* Master Remap Control Register */ 26af930827SMasahiro Yamada u32 filler[0x06]; 27af930827SMasahiro Yamada u32 ebicsa; /* EBI Chip Select Assignment Register */ 28af930827SMasahiro Yamada }; 29af930827SMasahiro Yamada 30af930827SMasahiro Yamada #endif /* __ASSEMBLY__ */ 31af930827SMasahiro Yamada 32af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 33af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 34af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_FOUR (2 << 0) 35af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 36af930827SMasahiro Yamada #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 37af930827SMasahiro Yamada 38af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 39af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 40af930827SMasahiro Yamada #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 41af930827SMasahiro Yamada #define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 42af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43af930827SMasahiro Yamada #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44af930827SMasahiro Yamada 45af930827SMasahiro Yamada #define AT91_MATRIX_M0PR_SHIFT 0 46af930827SMasahiro Yamada #define AT91_MATRIX_M1PR_SHIFT 4 47af930827SMasahiro Yamada #define AT91_MATRIX_M2PR_SHIFT 8 48af930827SMasahiro Yamada #define AT91_MATRIX_M3PR_SHIFT 12 49af930827SMasahiro Yamada #define AT91_MATRIX_M4PR_SHIFT 16 50af930827SMasahiro Yamada #define AT91_MATRIX_M5PR_SHIFT 20 51af930827SMasahiro Yamada 52af930827SMasahiro Yamada #define AT91_MATRIX_RCB0 (1 << 0) 53af930827SMasahiro Yamada #define AT91_MATRIX_RCB1 (1 << 1) 54af930827SMasahiro Yamada 55af930827SMasahiro Yamada #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 56af930827SMasahiro Yamada #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 57af930827SMasahiro Yamada #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 58af930827SMasahiro Yamada #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 59af930827SMasahiro Yamada #define AT91_MATRIX_DBPUC (1 << 8) 60af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 61af930827SMasahiro Yamada #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 62af930827SMasahiro Yamada 63af930827SMasahiro Yamada #endif 64