1 /*
2  * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h]
3  *
4  * Copyright (C) SAN People
5  * (C) Copyright 2010
6  * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
7  *
8  * Definitions for the SoCs:
9  * AT91SAM9261, AT91SAM9G10
10  *
11  * Note that those SoCs are mostly software and pin compatible,
12  * therefore this file applies to all of them. Differences between
13  * those SoCs are concentrated at the end of this file.
14  *
15  * SPDX-License-Identifier:	GPL-2.0+
16  */
17 
18 #ifndef AT91SAM9261_H
19 #define AT91SAM9261_H
20 
21 /*
22  * defines to be used in other places
23  */
24 #define CONFIG_AT91FAMILY	/* it's a member of AT91 */
25 
26 /*
27  * Peripheral identifiers/interrupts.
28  */
29 #define ATMEL_ID_FIQ	0	/* Advanced Interrupt Controller (FIQ) */
30 #define ATMEL_ID_SYS	1	/* System Peripherals */
31 #define ATMEL_ID_PIOA	2	/* Parallel IO Controller A */
32 #define ATMEL_ID_PIOB	3	/* Parallel IO Controller B */
33 #define ATMEL_ID_PIOC	4	/* Parallel IO Controller C */
34 /* Reserved:		5 */
35 #define ATMEL_ID_USART0	6	/* USART 0 */
36 #define ATMEL_ID_USART1	7	/* USART 1 */
37 #define ATMEL_ID_USART2	8	/* USART 2 */
38 #define ATMEL_ID_MCI	9	/* Multimedia Card Interface */
39 #define ATMEL_ID_UDP	10	/* USB Device Port */
40 #define ATMEL_ID_TWI0	11	/* Two-Wire Interface 0 */
41 #define ATMEL_ID_SPI0	12	/* Serial Peripheral Interface 0 */
42 #define ATMEL_ID_SPI1	13	/* Serial Peripheral Interface 1 */
43 #define ATMEL_ID_SSC0	14	/* Serial Synchronous Controller 0 */
44 #define ATMEL_ID_SSC1	15	/* Serial Synchronous Controller 1 */
45 #define ATMEL_ID_SSC2	16	/* Serial Synchronous Controller 2 */
46 #define ATMEL_ID_TC0	17	/* Timer Counter 0 */
47 #define ATMEL_ID_TC1	18	/* Timer Counter 1 */
48 #define ATMEL_ID_TC2	19	/* Timer Counter 2 */
49 #define ATMEL_ID_UHP	20	/* USB Host port */
50 #define ATMEL_ID_LCDC	21	/* LDC Controller */
51 /* Reserved:		22-28 */
52 #define ATMEL_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
53 #define ATMEL_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
54 #define ATMEL_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
55 
56 /*
57  * User Peripherals physical base addresses.
58  */
59 #define ATMEL_BASE_TCB0		0xfffa0000
60 #define ATMEL_BASE_TC0		0xfffa0000
61 #define ATMEL_BASE_TC1		0xfffa0040
62 #define ATMEL_BASE_TC2		0xfffa0080
63 #define ATMEL_BASE_UDP0		0xfffa4000
64 #define ATMEL_BASE_MCI		0xfffa8000
65 #define ATMEL_BASE_TWI0		0xfffac000
66 #define ATMEL_BASE_USART0	0xfffb0000
67 #define ATMEL_BASE_USART1	0xfffb4000
68 #define ATMEL_BASE_USART2	0xfffb8000
69 #define ATMEL_BASE_SSC0		0xfffbc000
70 #define ATMEL_BASE_SSC1		0xfffc0000
71 #define ATMEL_BASE_SSC2		0xfffc4000
72 #define ATMEL_BASE_SPI0		0xfffc8000
73 #define ATMEL_BASE_SPI1		0xfffcc000
74 /* Reserved:	0xfffc4000 - 0xffffe9ff */
75 
76 /*
77  * System Peripherals physical base addresses.
78  */
79 #define ATMEL_BASE_SYS		0xffffea00
80 #define ATMEL_BASE_SDRAMC	0xffffea00
81 #define ATMEL_BASE_SMC		0xffffec00
82 #define ATMEL_BASE_MATRIX	0xffffee00
83 #define ATMEL_BASE_AIC		0xfffff000
84 #define ATMEL_BASE_DBGU		0xfffff200
85 #define ATMEL_BASE_PIOA		0xfffff400
86 #define ATMEL_BASE_PIOB		0xfffff600
87 #define ATMEL_BASE_PIOC		0xfffff800
88 #define ATMEL_BASE_PMC		0xfffffc00
89 #define ATMEL_BASE_RSTC		0xfffffd00
90 #define ATMEL_BASE_SHDWN	0xfffffd10
91 #define ATMEL_BASE_RTT		0xfffffd20
92 #define ATMEL_BASE_PIT		0xfffffd30
93 #define ATMEL_BASE_WDT		0xfffffd40
94 #define ATMEL_BASE_GPBR		0xfffffd50
95 
96 /*
97  * Internal Memory common on all these SoCs
98  */
99 #define ATMEL_BASE_SRAM		0x00300000	/* Internal SRAM base address */
100 #define ATMEL_SIZE_SRAM		0x00028000	/* Internal SRAM size (160Kb) */
101 
102 #define ATMEL_BASE_ROM		0x00400000	/* Internal ROM base address */
103 #define ATMEL_SIZE_ROM		0x00008000	/* Internal ROM size (32Kb) */
104 
105 #define ATMEL_BASE_UHP		0x00500000	/* USB Host controller */
106 #define ATMEL_BASE_LCDC		0x00600000	/* LDC controller */
107 
108 /*
109  * External memory
110  */
111 #define ATMEL_BASE_CS0		0x10000000	/* typically NOR */
112 #define ATMEL_BASE_CS1		0x20000000	/* SDRAM */
113 #define ATMEL_BASE_CS2		0x30000000
114 #define ATMEL_BASE_CS3		0x40000000	/* typically NAND */
115 #define ATMEL_BASE_CS4		0x50000000
116 #define ATMEL_BASE_CS5		0x60000000
117 #define ATMEL_BASE_CS6		0x70000000
118 #define ATMEL_BASE_CS7		0x80000000
119 
120 /*
121  * Other misc defines
122  */
123 #define ATMEL_PIO_PORTS		3		/* theese SoCs have 3 PIO */
124 #define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
125 #define ATMEL_BASE_PIO		ATMEL_BASE_PIOA
126 
127 /*
128  * SoC specific defines
129  */
130 #if defined(CONFIG_AT91SAM9261)
131 # define ATMEL_CPU_NAME		"AT91SAM9261"
132 #elif defined(CONFIG_AT91SAM9G10)
133 # define ATMEL_CPU_NAME		"AT91SAM9G10"
134 #endif
135 
136 #endif
137