1 /* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] 3 * 4 * Copyright (C) SAN People 5 * (C) Copyright 2010 6 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 7 * 8 * Definitions for the SoCs: 9 * AT91SAM9261, AT91SAM9G10 10 * 11 * Note that those SoCs are mostly software and pin compatible, 12 * therefore this file applies to all of them. Differences between 13 * those SoCs are concentrated at the end of this file. 14 * 15 * SPDX-License-Identifier: GPL-2.0+ 16 */ 17 18 #ifndef AT91SAM9261_H 19 #define AT91SAM9261_H 20 21 /* 22 * Peripheral identifiers/interrupts. 23 */ 24 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 25 #define ATMEL_ID_SYS 1 /* System Peripherals */ 26 #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 27 #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 28 #define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ 29 /* Reserved: 5 */ 30 #define ATMEL_ID_USART0 6 /* USART 0 */ 31 #define ATMEL_ID_USART1 7 /* USART 1 */ 32 #define ATMEL_ID_USART2 8 /* USART 2 */ 33 #define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ 34 #define ATMEL_ID_UDP 10 /* USB Device Port */ 35 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ 36 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 37 #define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 38 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 39 #define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 40 #define ATMEL_ID_SSC2 16 /* Serial Synchronous Controller 2 */ 41 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */ 42 #define ATMEL_ID_TC1 18 /* Timer Counter 1 */ 43 #define ATMEL_ID_TC2 19 /* Timer Counter 2 */ 44 #define ATMEL_ID_UHP 20 /* USB Host port */ 45 #define ATMEL_ID_LCDC 21 /* LDC Controller */ 46 /* Reserved: 22-28 */ 47 #define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 48 #define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 49 #define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 50 51 /* 52 * User Peripherals physical base addresses. 53 */ 54 #define ATMEL_BASE_TCB0 0xfffa0000 55 #define ATMEL_BASE_TC0 0xfffa0000 56 #define ATMEL_BASE_TC1 0xfffa0040 57 #define ATMEL_BASE_TC2 0xfffa0080 58 #define ATMEL_BASE_UDP0 0xfffa4000 59 #define ATMEL_BASE_MCI 0xfffa8000 60 #define ATMEL_BASE_TWI0 0xfffac000 61 #define ATMEL_BASE_USART0 0xfffb0000 62 #define ATMEL_BASE_USART1 0xfffb4000 63 #define ATMEL_BASE_USART2 0xfffb8000 64 #define ATMEL_BASE_SSC0 0xfffbc000 65 #define ATMEL_BASE_SSC1 0xfffc0000 66 #define ATMEL_BASE_SSC2 0xfffc4000 67 #define ATMEL_BASE_SPI0 0xfffc8000 68 #define ATMEL_BASE_SPI1 0xfffcc000 69 /* Reserved: 0xfffc4000 - 0xffffe9ff */ 70 71 /* 72 * System Peripherals physical base addresses. 73 */ 74 #define ATMEL_BASE_SYS 0xffffea00 75 #define ATMEL_BASE_SDRAMC 0xffffea00 76 #define ATMEL_BASE_SMC 0xffffec00 77 #define ATMEL_BASE_MATRIX 0xffffee00 78 #define ATMEL_BASE_AIC 0xfffff000 79 #define ATMEL_BASE_DBGU 0xfffff200 80 #define ATMEL_BASE_PIOA 0xfffff400 81 #define ATMEL_BASE_PIOB 0xfffff600 82 #define ATMEL_BASE_PIOC 0xfffff800 83 #define ATMEL_BASE_PMC 0xfffffc00 84 #define ATMEL_BASE_RSTC 0xfffffd00 85 #define ATMEL_BASE_SHDWN 0xfffffd10 86 #define ATMEL_BASE_RTT 0xfffffd20 87 #define ATMEL_BASE_PIT 0xfffffd30 88 #define ATMEL_BASE_WDT 0xfffffd40 89 #define ATMEL_BASE_GPBR 0xfffffd50 90 91 /* 92 * Internal Memory common on all these SoCs 93 */ 94 #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ 95 #define ATMEL_SIZE_SRAM 0x00028000 /* Internal SRAM size (160Kb) */ 96 97 #define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ 98 #define ATMEL_SIZE_ROM 0x00008000 /* Internal ROM size (32Kb) */ 99 100 #define ATMEL_BASE_UHP 0x00500000 /* USB Host controller */ 101 #define ATMEL_BASE_LCDC 0x00600000 /* LDC controller */ 102 103 /* 104 * External memory 105 */ 106 #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ 107 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 108 #define ATMEL_BASE_CS2 0x30000000 109 #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ 110 #define ATMEL_BASE_CS4 0x50000000 111 #define ATMEL_BASE_CS5 0x60000000 112 #define ATMEL_BASE_CS6 0x70000000 113 #define ATMEL_BASE_CS7 0x80000000 114 115 /* Timer */ 116 #define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c 117 118 /* 119 * Other misc defines 120 */ 121 #define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ 122 #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 123 #define ATMEL_BASE_PIO ATMEL_BASE_PIOA 124 125 /* 126 * SoC specific defines 127 */ 128 #if defined(CONFIG_AT91SAM9261) 129 # define ATMEL_CPU_NAME "AT91SAM9261" 130 #elif defined(CONFIG_AT91SAM9G10) 131 # define ATMEL_CPU_NAME "AT91SAM9G10" 132 #endif 133 134 #endif 135