1 /* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] 3 * 4 * (C) 2006 Andrew Victor 5 * (C) Copyright 2010 6 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de 7 * 8 * Definitions for the SoCs: 9 * AT91SAM9260, AT91SAM9G20, AT91SAM9XE 10 * 11 * Note that those SoCs are mostly software and pin compatible, 12 * therefore this file applies to all of them. Differences between 13 * those SoCs are concentrated at the end of this file. 14 * 15 * SPDX-License-Identifier: GPL-2.0+ 16 */ 17 18 #ifndef AT91SAM9260_H 19 #define AT91SAM9260_H 20 21 /* 22 * defines to be used in other places 23 */ 24 #define CONFIG_AT91FAMILY /* it's a member of AT91 */ 25 26 /* 27 * Peripheral identifiers/interrupts. 28 */ 29 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 30 #define ATMEL_ID_SYS 1 /* System Peripherals */ 31 #define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ 32 #define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ 33 #define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ 34 #define ATMEL_ID_ADC 5 /* Analog-to-Digital Converter */ 35 #define ATMEL_ID_USART0 6 /* USART 0 */ 36 #define ATMEL_ID_USART1 7 /* USART 1 */ 37 #define ATMEL_ID_USART2 8 /* USART 2 */ 38 #define ATMEL_ID_MCI 9 /* Multimedia Card Interface */ 39 #define ATMEL_ID_UDP 10 /* USB Device Port */ 40 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */ 41 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */ 42 #define ATMEL_ID_SPI1 13 /* Serial Peripheral Interface 1 */ 43 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 44 /* Reserved: 15 */ 45 /* Reserved: 16 */ 46 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */ 47 #define ATMEL_ID_TC1 18 /* Timer Counter 1 */ 48 #define ATMEL_ID_TC2 19 /* Timer Counter 2 */ 49 #define ATMEL_ID_UHP 20 /* USB Host port */ 50 #define ATMEL_ID_EMAC0 21 /* Ethernet 0 */ 51 #define ATMEL_ID_ISI 22 /* Image Sensor Interface */ 52 #define ATMEL_ID_USART3 23 /* USART 3 */ 53 #define ATMEL_ID_USART4 24 /* USART 4 */ 54 /* USART5 or TWI1: 25 */ 55 #define ATMEL_ID_TC3 26 /* Timer Counter 3 */ 56 #define ATMEL_ID_TC4 27 /* Timer Counter 4 */ 57 #define ATMEL_ID_TC5 28 /* Timer Counter 5 */ 58 #define ATMEL_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ 59 #define ATMEL_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ 60 #define ATMEL_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ 61 62 /* 63 * User Peripherals physical base addresses. 64 */ 65 #define ATMEL_BASE_TCB0 0xfffa0000 66 #define ATMEL_BASE_TC0 0xfffa0000 67 #define ATMEL_BASE_TC1 0xfffa0040 68 #define ATMEL_BASE_TC2 0xfffa0080 69 #define ATMEL_BASE_UDP0 0xfffa4000 70 #define ATMEL_BASE_MCI 0xfffa8000 71 #define ATMEL_BASE_TWI0 0xfffac000 72 #define ATMEL_BASE_USART0 0xfffb0000 73 #define ATMEL_BASE_USART1 0xfffb4000 74 #define ATMEL_BASE_USART2 0xfffb8000 75 #define ATMEL_BASE_SSC0 0xfffbc000 76 #define ATMEL_BASE_ISI0 0xfffc0000 77 #define ATMEL_BASE_EMAC0 0xfffc4000 78 #define ATMEL_BASE_SPI0 0xfffc8000 79 #define ATMEL_BASE_SPI1 0xfffcc000 80 #define ATMEL_BASE_USART3 0xfffd0000 81 #define ATMEL_BASE_USART4 0xfffd4000 82 /* USART5 or TWI1: 0xfffd8000 */ 83 #define ATMEL_BASE_TCB1 0xfffdc000 84 #define ATMEL_BASE_TC3 0xfffdc000 85 #define ATMEL_BASE_TC4 0xfffdc040 86 #define ATMEL_BASE_TC5 0xfffdc080 87 #define ATMEL_BASE_ADC 0xfffe0000 88 /* Reserved: 0xfffe4000 - 0xffffe7ff */ 89 90 /* 91 * System Peripherals physical base addresses. 92 */ 93 #define ATMEL_BASE_SYS 0xffffe800 94 #define ATMEL_BASE_SDRAMC 0xffffea00 95 #define ATMEL_BASE_SMC 0xffffec00 96 #define ATMEL_BASE_MATRIX 0xffffee00 97 #define ATMEL_BASE_CCFG 0xffffef14 98 #define ATMEL_BASE_AIC 0xfffff000 99 #define ATMEL_BASE_DBGU 0xfffff200 100 #define ATMEL_BASE_PIOA 0xfffff400 101 #define ATMEL_BASE_PIOB 0xfffff600 102 #define ATMEL_BASE_PIOC 0xfffff800 103 /* EEFC: 0xfffffa00 */ 104 #define ATMEL_BASE_PMC 0xfffffc00 105 #define ATMEL_BASE_RSTC 0xfffffd00 106 #define ATMEL_BASE_SHDWN 0xfffffd10 107 #define ATMEL_BASE_RTT 0xfffffd20 108 #define ATMEL_BASE_PIT 0xfffffd30 109 #define ATMEL_BASE_WDT 0xfffffd40 110 /* GPBR(non-XE SoCs): 0xfffffd50 */ 111 /* GPBR(XE SoCs): 0xfffffd60 */ 112 /* Reserved: 0xfffffd70 - 0xffffffff */ 113 114 /* 115 * Internal Memory common on all these SoCs 116 */ 117 #define ATMEL_BASE_BOOT 0x00000000 /* Boot mapped area */ 118 #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ 119 /* SRAM or FLASH: 0x00200000 */ 120 /* SRAM: 0x00300000 */ 121 /* Reserved: 0x00400000 */ 122 #define ATMEL_UHP_BASE 0x00500000 /* USB Host controller */ 123 124 /* 125 * External memory 126 */ 127 #define ATMEL_BASE_CS0 0x10000000 /* typically NOR */ 128 #define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ 129 #define ATMEL_BASE_CS2 0x30000000 130 #define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ 131 #define ATMEL_BASE_CS4 0x50000000 132 #define ATMEL_BASE_CS5 0x60000000 133 #define ATMEL_BASE_CS6 0x70000000 134 #define ATMEL_BASE_CS7 0x80000000 135 136 /* 137 * Other misc defines 138 */ 139 #ifndef CONFIG_DM_GPIO 140 #define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */ 141 #define ATMEL_BASE_PIO ATMEL_BASE_PIOA 142 #endif 143 #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 144 145 /* 146 * SoC specific defines 147 */ 148 #if defined(CONFIG_AT91SAM9XE) 149 # define ATMEL_CPU_NAME "AT91SAM9XE" 150 # define ATMEL_ID_TWI1 25 /* TWI 1 */ 151 # define ATMEL_BASE_FLASH 0x00200000 /* Internal FLASH */ 152 # define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM */ 153 # define ATMEL_BASE_TWI1 0xfffd8000 154 # define ATMEL_BASE_EEFC 0xfffffa00 155 # define ATMEL_BASE_GPBR 0xfffffd60 156 #elif defined(CONFIG_AT91SAM9260) 157 # define ATMEL_CPU_NAME "AT91SAM9260" 158 # define ATMEL_ID_USART5 25 /* USART 5 */ 159 # define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ 160 # define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ 161 # define ATMEL_BASE_USART5 0xfffd8000 162 # define ATMEL_BASE_GPBR 0xfffffd50 163 #elif defined(CONFIG_AT91SAM9G20) 164 # define ATMEL_CPU_NAME "AT91SAM9G20" 165 # define ATMEL_ID_USART5 25 /* USART 5 */ 166 # define ATMEL_BASE_SRAM0 0x00200000 /* Internal SRAM 0 */ 167 # define ATMEL_BASE_SRAM1 0x00300000 /* Internal SRAM 1 */ 168 # define ATMEL_BASE_USART5 0xfffd8000 169 # define ATMEL_BASE_GPBR 0xfffffd50 170 #endif 171 172 #endif 173