1*af930827SMasahiro Yamada /* 2*af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h] 3*af930827SMasahiro Yamada * 4*af930827SMasahiro Yamada * Copyright (C) 2005 Ivan Kokshaysky 5*af930827SMasahiro Yamada * Copyright (C) SAN People 6*af930827SMasahiro Yamada * 7*af930827SMasahiro Yamada * Serial Peripheral Interface (SPI) registers. 8*af930827SMasahiro Yamada * Based on AT91RM9200 datasheet revision E. 9*af930827SMasahiro Yamada * 10*af930827SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 11*af930827SMasahiro Yamada */ 12*af930827SMasahiro Yamada 13*af930827SMasahiro Yamada #ifndef AT91_SPI_H 14*af930827SMasahiro Yamada #define AT91_SPI_H 15*af930827SMasahiro Yamada 16*af930827SMasahiro Yamada #include <asm/arch/at91_pdc.h> 17*af930827SMasahiro Yamada 18*af930827SMasahiro Yamada typedef struct at91_spi { 19*af930827SMasahiro Yamada u32 cr; /* 0x00 Control Register */ 20*af930827SMasahiro Yamada u32 mr; /* 0x04 Mode Register */ 21*af930827SMasahiro Yamada u32 rdr; /* 0x08 Receive Data Register */ 22*af930827SMasahiro Yamada u32 tdr; /* 0x0C Transmit Data Register */ 23*af930827SMasahiro Yamada u32 sr; /* 0x10 Status Register */ 24*af930827SMasahiro Yamada u32 ier; /* 0x14 Interrupt Enable Register */ 25*af930827SMasahiro Yamada u32 idr; /* 0x18 Interrupt Disable Register */ 26*af930827SMasahiro Yamada u32 imr; /* 0x1C Interrupt Mask Register */ 27*af930827SMasahiro Yamada u32 reserve1[4]; 28*af930827SMasahiro Yamada u32 csr[4]; /* 0x30 Chip Select Register 0-3 */ 29*af930827SMasahiro Yamada u32 reserve2[48]; 30*af930827SMasahiro Yamada at91_pdc_t pdc; 31*af930827SMasahiro Yamada } at91_spi_t; 32*af930827SMasahiro Yamada 33*af930827SMasahiro Yamada #ifdef CONFIG_ATMEL_LEGACY 34*af930827SMasahiro Yamada 35*af930827SMasahiro Yamada #define AT91_SPI_CR 0x00 /* Control Register */ 36*af930827SMasahiro Yamada #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ 37*af930827SMasahiro Yamada #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ 38*af930827SMasahiro Yamada #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ 39*af930827SMasahiro Yamada #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ 40*af930827SMasahiro Yamada 41*af930827SMasahiro Yamada #define AT91_SPI_MR 0x04 /* Mode Register */ 42*af930827SMasahiro Yamada #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ 43*af930827SMasahiro Yamada #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ 44*af930827SMasahiro Yamada #define AT91_SPI_PS_FIXED (0 << 1) 45*af930827SMasahiro Yamada #define AT91_SPI_PS_VARIABLE (1 << 1) 46*af930827SMasahiro Yamada #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ 47*af930827SMasahiro Yamada #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ 48*af930827SMasahiro Yamada #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ 49*af930827SMasahiro Yamada #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ 50*af930827SMasahiro Yamada #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 51*af930827SMasahiro Yamada #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ 52*af930827SMasahiro Yamada 53*af930827SMasahiro Yamada #define AT91_SPI_RDR 0x08 /* Receive Data Register */ 54*af930827SMasahiro Yamada #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ 55*af930827SMasahiro Yamada #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 56*af930827SMasahiro Yamada 57*af930827SMasahiro Yamada #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ 58*af930827SMasahiro Yamada #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ 59*af930827SMasahiro Yamada #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ 60*af930827SMasahiro Yamada #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ 61*af930827SMasahiro Yamada 62*af930827SMasahiro Yamada #define AT91_SPI_SR 0x10 /* Status Register */ 63*af930827SMasahiro Yamada #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ 64*af930827SMasahiro Yamada #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ 65*af930827SMasahiro Yamada #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ 66*af930827SMasahiro Yamada #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ 67*af930827SMasahiro Yamada #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ 68*af930827SMasahiro Yamada #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ 69*af930827SMasahiro Yamada #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ 70*af930827SMasahiro Yamada #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ 71*af930827SMasahiro Yamada #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ 72*af930827SMasahiro Yamada #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ 73*af930827SMasahiro Yamada #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ 74*af930827SMasahiro Yamada 75*af930827SMasahiro Yamada #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ 76*af930827SMasahiro Yamada #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ 77*af930827SMasahiro Yamada #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ 78*af930827SMasahiro Yamada 79*af930827SMasahiro Yamada #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ 80*af930827SMasahiro Yamada #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ 81*af930827SMasahiro Yamada #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ 82*af930827SMasahiro Yamada #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ 83*af930827SMasahiro Yamada #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ 84*af930827SMasahiro Yamada #define AT91_SPI_BITS_8 (0 << 4) 85*af930827SMasahiro Yamada #define AT91_SPI_BITS_9 (1 << 4) 86*af930827SMasahiro Yamada #define AT91_SPI_BITS_10 (2 << 4) 87*af930827SMasahiro Yamada #define AT91_SPI_BITS_11 (3 << 4) 88*af930827SMasahiro Yamada #define AT91_SPI_BITS_12 (4 << 4) 89*af930827SMasahiro Yamada #define AT91_SPI_BITS_13 (5 << 4) 90*af930827SMasahiro Yamada #define AT91_SPI_BITS_14 (6 << 4) 91*af930827SMasahiro Yamada #define AT91_SPI_BITS_15 (7 << 4) 92*af930827SMasahiro Yamada #define AT91_SPI_BITS_16 (8 << 4) 93*af930827SMasahiro Yamada #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ 94*af930827SMasahiro Yamada #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ 95*af930827SMasahiro Yamada #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ 96*af930827SMasahiro Yamada 97*af930827SMasahiro Yamada #define AT91_SPI_RPR 0x0100 /* Receive Pointer Register */ 98*af930827SMasahiro Yamada 99*af930827SMasahiro Yamada #define AT91_SPI_RCR 0x0104 /* Receive Counter Register */ 100*af930827SMasahiro Yamada 101*af930827SMasahiro Yamada #define AT91_SPI_TPR 0x0108 /* Transmit Pointer Register */ 102*af930827SMasahiro Yamada 103*af930827SMasahiro Yamada #define AT91_SPI_TCR 0x010c /* Transmit Counter Register */ 104*af930827SMasahiro Yamada 105*af930827SMasahiro Yamada #define AT91_SPI_RNPR 0x0110 /* Receive Next Pointer Register */ 106*af930827SMasahiro Yamada 107*af930827SMasahiro Yamada #define AT91_SPI_RNCR 0x0114 /* Receive Next Counter Register */ 108*af930827SMasahiro Yamada 109*af930827SMasahiro Yamada #define AT91_SPI_TNPR 0x0118 /* Transmit Next Pointer Register */ 110*af930827SMasahiro Yamada 111*af930827SMasahiro Yamada #define AT91_SPI_TNCR 0x011c /* Transmit Next Counter Register */ 112*af930827SMasahiro Yamada 113*af930827SMasahiro Yamada #define AT91_SPI_PTCR 0x0120 /* PDC Transfer Control Register */ 114*af930827SMasahiro Yamada #define AT91_SPI_RXTEN (0x1 << 0) /* Receiver Transfer Enable */ 115*af930827SMasahiro Yamada #define AT91_SPI_RXTDIS (0x1 << 1) /* Receiver Transfer Disable */ 116*af930827SMasahiro Yamada #define AT91_SPI_TXTEN (0x1 << 8) /* Transmitter Transfer Enable */ 117*af930827SMasahiro Yamada #define AT91_SPI_TXTDIS (0x1 << 9) /* Transmitter Transfer Disable */ 118*af930827SMasahiro Yamada 119*af930827SMasahiro Yamada #define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */ 120*af930827SMasahiro Yamada 121*af930827SMasahiro Yamada #endif /* CONFIG_ATMEL_LEGACY */ 122*af930827SMasahiro Yamada 123*af930827SMasahiro Yamada #endif 124