1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] 4af930827SMasahiro Yamada * 5af930827SMasahiro Yamada * Copyright (C) 2005 Ivan Kokshaysky 6af930827SMasahiro Yamada * Copyright (C) SAN People 7af930827SMasahiro Yamada * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 8af930827SMasahiro Yamada * 9af930827SMasahiro Yamada * Parallel I/O Controller (PIO) - System peripherals registers. 10af930827SMasahiro Yamada * Based on AT91RM9200 datasheet revision E. 11af930827SMasahiro Yamada */ 12af930827SMasahiro Yamada 13af930827SMasahiro Yamada #ifndef AT91_PIO_H 14af930827SMasahiro Yamada #define AT91_PIO_H 15af930827SMasahiro Yamada 16af930827SMasahiro Yamada 17af930827SMasahiro Yamada #define AT91_ASM_PIO_RANGE 0x200 18af930827SMasahiro Yamada #define AT91_ASM_PIOC_ASR \ 19af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) 20af930827SMasahiro Yamada #define AT91_ASM_PIOC_BSR \ 21af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x74) 22af930827SMasahiro Yamada #define AT91_ASM_PIOC_PDR \ 23af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x04) 24af930827SMasahiro Yamada #define AT91_ASM_PIOC_PUDR \ 25af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x60) 26af930827SMasahiro Yamada 27af930827SMasahiro Yamada #define AT91_ASM_PIOD_PDR \ 28af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x04) 29af930827SMasahiro Yamada #define AT91_ASM_PIOD_PUDR \ 30af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x60) 31af930827SMasahiro Yamada #define AT91_ASM_PIOD_ASR \ 32af930827SMasahiro Yamada (ATMEL_BASE_PIO + AT91_PIO_PORTD * AT91_ASM_PIO_RANGE + 0x70) 33af930827SMasahiro Yamada 342dc63f73SWenyou Yang #define PIO_SCDR_DIV 0x3fff /* Slow Clock Divider Selection for Debouncing Mask */ 352dc63f73SWenyou Yang 36af930827SMasahiro Yamada #ifndef __ASSEMBLY__ 37af930827SMasahiro Yamada 38af930827SMasahiro Yamada typedef struct at91_port { 39af930827SMasahiro Yamada u32 per; /* 0x00 PIO Enable Register */ 40af930827SMasahiro Yamada u32 pdr; /* 0x04 PIO Disable Register */ 41af930827SMasahiro Yamada u32 psr; /* 0x08 PIO Status Register */ 42af930827SMasahiro Yamada u32 reserved0; 43af930827SMasahiro Yamada u32 oer; /* 0x10 Output Enable Register */ 44af930827SMasahiro Yamada u32 odr; /* 0x14 Output Disable Registerr */ 45af930827SMasahiro Yamada u32 osr; /* 0x18 Output Status Register */ 46af930827SMasahiro Yamada u32 reserved1; 47af930827SMasahiro Yamada u32 ifer; /* 0x20 Input Filter Enable Register */ 48af930827SMasahiro Yamada u32 ifdr; /* 0x24 Input Filter Disable Register */ 49af930827SMasahiro Yamada u32 ifsr; /* 0x28 Input Filter Status Register */ 50af930827SMasahiro Yamada u32 reserved2; 51af930827SMasahiro Yamada u32 sodr; /* 0x30 Set Output Data Register */ 52af930827SMasahiro Yamada u32 codr; /* 0x34 Clear Output Data Register */ 53af930827SMasahiro Yamada u32 odsr; /* 0x38 Output Data Status Register */ 54af930827SMasahiro Yamada u32 pdsr; /* 0x3C Pin Data Status Register */ 55af930827SMasahiro Yamada u32 ier; /* 0x40 Interrupt Enable Register */ 56af930827SMasahiro Yamada u32 idr; /* 0x44 Interrupt Disable Register */ 57af930827SMasahiro Yamada u32 imr; /* 0x48 Interrupt Mask Register */ 58af930827SMasahiro Yamada u32 isr; /* 0x4C Interrupt Status Register */ 59af930827SMasahiro Yamada u32 mder; /* 0x50 Multi-driver Enable Register */ 60af930827SMasahiro Yamada u32 mddr; /* 0x54 Multi-driver Disable Register */ 61af930827SMasahiro Yamada u32 mdsr; /* 0x58 Multi-driver Status Register */ 62af930827SMasahiro Yamada u32 reserved3; 63af930827SMasahiro Yamada u32 pudr; /* 0x60 Pull-up Disable Register */ 64af930827SMasahiro Yamada u32 puer; /* 0x64 Pull-up Enable Register */ 65af930827SMasahiro Yamada u32 pusr; /* 0x68 Pad Pull-up Status Register */ 66af930827SMasahiro Yamada u32 reserved4; 672dc63f73SWenyou Yang union { 682dc63f73SWenyou Yang struct { 69af930827SMasahiro Yamada u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ 70af930827SMasahiro Yamada u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ 71af930827SMasahiro Yamada u32 reserved5[2]; 72af930827SMasahiro Yamada u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ 73af930827SMasahiro Yamada u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ 74af930827SMasahiro Yamada u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ 75af930827SMasahiro Yamada u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ 76af930827SMasahiro Yamada u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ 77af930827SMasahiro Yamada u32 ppder; /* 0x94 Pad Pull-down Enable Register */ 78af930827SMasahiro Yamada u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ 79af930827SMasahiro Yamada u32 reserved6; /* */ 802dc63f73SWenyou Yang } pio3; 812dc63f73SWenyou Yang 822dc63f73SWenyou Yang struct { 83af930827SMasahiro Yamada u32 asr; /* 0x70 Select A Register */ 84af930827SMasahiro Yamada u32 bsr; /* 0x74 Select B Register */ 85af930827SMasahiro Yamada u32 absr; /* 0x78 AB Select Status Register */ 86af930827SMasahiro Yamada u32 reserved5[9]; /* */ 872dc63f73SWenyou Yang } pio2; 882dc63f73SWenyou Yang } mux; 892dc63f73SWenyou Yang 90af930827SMasahiro Yamada u32 ower; /* 0xA0 Output Write Enable Register */ 91af930827SMasahiro Yamada u32 owdr; /* 0xA4 Output Write Disable Register */ 92af930827SMasahiro Yamada u32 owsr; /* OxA8 Output Write Status Register */ 93af930827SMasahiro Yamada u32 reserved7; /* */ 94af930827SMasahiro Yamada u32 aimer; /* 0xB0 Additional INT Modes Enable Register */ 95af930827SMasahiro Yamada u32 aimdr; /* 0xB4 Additional INT Modes Disable Register */ 96af930827SMasahiro Yamada u32 aimmr; /* 0xB8 Additional INT Modes Mask Register */ 97af930827SMasahiro Yamada u32 reserved8; /* */ 98af930827SMasahiro Yamada u32 esr; /* 0xC0 Edge Select Register */ 99af930827SMasahiro Yamada u32 lsr; /* 0xC4 Level Select Register */ 100af930827SMasahiro Yamada u32 elsr; /* 0xC8 Edge/Level Status Register */ 101af930827SMasahiro Yamada u32 reserved9; /* 0xCC */ 102af930827SMasahiro Yamada u32 fellsr; /* 0xD0 Falling /Low Level Select Register */ 103af930827SMasahiro Yamada u32 rehlsr; /* 0xD4 Rising /High Level Select Register */ 104af930827SMasahiro Yamada u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ 105af930827SMasahiro Yamada u32 reserved10; /* */ 106af930827SMasahiro Yamada u32 locksr; /* 0xE0 Lock Status */ 107af930827SMasahiro Yamada u32 wpmr; /* 0xE4 Write Protect Mode Register */ 108af930827SMasahiro Yamada u32 wpsr; /* 0xE8 Write Protect Status Register */ 109af930827SMasahiro Yamada u32 reserved11[5]; /* */ 110af930827SMasahiro Yamada u32 schmitt; /* 0x100 Schmitt Trigger Register */ 1119319a756SWenyou Yang u32 reserved12[4]; /* 0x104 ~ 0x110 */ 1129319a756SWenyou Yang u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */ 1139319a756SWenyou Yang u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */ 1149319a756SWenyou Yang u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */ 1159319a756SWenyou Yang u32 reserved13[12]; /* 0x120 ~ 0x14C */ 116af930827SMasahiro Yamada } at91_port_t; 117af930827SMasahiro Yamada 118af930827SMasahiro Yamada typedef union at91_pio { 119af930827SMasahiro Yamada struct { 120af930827SMasahiro Yamada at91_port_t pioa; 121af930827SMasahiro Yamada at91_port_t piob; 122af930827SMasahiro Yamada at91_port_t pioc; 123af930827SMasahiro Yamada at91_port_t piod; /* not present in all hardware */ 124af930827SMasahiro Yamada at91_port_t pioe;/* not present in all hardware */ 125af930827SMasahiro Yamada }; 126af930827SMasahiro Yamada at91_port_t port[5]; 127af930827SMasahiro Yamada } at91_pio_t; 128af930827SMasahiro Yamada 129af930827SMasahiro Yamada #ifdef CONFIG_AT91_GPIO 130af930827SMasahiro Yamada int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); 131af930827SMasahiro Yamada int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); 132af930827SMasahiro Yamada int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); 133af930827SMasahiro Yamada int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); 134af930827SMasahiro Yamada int at91_set_pio_output(unsigned port, unsigned pin, int value); 135af930827SMasahiro Yamada int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup); 136af930827SMasahiro Yamada int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); 137af930827SMasahiro Yamada int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on); 138af930827SMasahiro Yamada int at91_set_pio_value(unsigned port, unsigned pin, int value); 139af930827SMasahiro Yamada int at91_get_pio_value(unsigned port, unsigned pin); 1402dc63f73SWenyou Yang 1412dc63f73SWenyou Yang int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup); 1422dc63f73SWenyou Yang int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup); 1432dc63f73SWenyou Yang int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup); 1442dc63f73SWenyou Yang int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup); 1452dc63f73SWenyou Yang int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); 1462dc63f73SWenyou Yang int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup); 1472dc63f73SWenyou Yang int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on); 1482dc63f73SWenyou Yang int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); 149af930827SMasahiro Yamada #endif 150af930827SMasahiro Yamada #endif 151af930827SMasahiro Yamada 152af930827SMasahiro Yamada #define AT91_PIO_PORTA 0x0 153af930827SMasahiro Yamada #define AT91_PIO_PORTB 0x1 154af930827SMasahiro Yamada #define AT91_PIO_PORTC 0x2 155af930827SMasahiro Yamada #define AT91_PIO_PORTD 0x3 156af930827SMasahiro Yamada #define AT91_PIO_PORTE 0x4 157af930827SMasahiro Yamada 158af930827SMasahiro Yamada #endif 159