1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 4 */ 5 6 #ifndef AT91_MATRIX_H 7 #define AT91_MATRIX_H 8 9 #ifdef __ASSEMBLY__ 10 11 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 12 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) 13 #elif defined(CONFIG_AT91SAM9261) 14 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) 15 #elif defined(CONFIG_AT91SAM9263) 16 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) 17 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 18 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) 19 #else 20 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU 21 #endif 22 23 #define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX 24 25 #else 26 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 27 #define AT91_MATRIX_MASTERS 6 28 #define AT91_MATRIX_SLAVES 5 29 #elif defined(CONFIG_AT91SAM9261) 30 #define AT91_MATRIX_MASTERS 1 31 #define AT91_MATRIX_SLAVES 5 32 #elif defined(CONFIG_AT91SAM9263) 33 #define AT91_MATRIX_MASTERS 9 34 #define AT91_MATRIX_SLAVES 7 35 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 36 #define AT91_MATRIX_MASTERS 11 37 #define AT91_MATRIX_SLAVES 8 38 #else 39 #error CPU not supported. Please update at91_matrix.h 40 #endif 41 42 typedef struct at91_priority { 43 u32 a; 44 u32 b; 45 } at91_priority_t; 46 47 typedef struct at91_matrix { 48 u32 mcfg[AT91_MATRIX_MASTERS]; 49 #if defined(CONFIG_AT91SAM9261) 50 u32 scfg[AT91_MATRIX_SLAVES]; 51 u32 res61_1[3]; 52 u32 tcr; 53 u32 res61_2[2]; 54 u32 csa; 55 u32 pucr; 56 u32 res61_3[114]; 57 #else 58 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 59 u32 scfg[AT91_MATRIX_SLAVES]; 60 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 61 at91_priority_t pr[AT91_MATRIX_SLAVES]; 62 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 63 u32 mrcr; /* 0x100 Master Remap Control */ 64 u32 reserve4[3]; 65 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 67 u32 womr; /* 0x1E4 Write Protect Mode */ 68 u32 wpsr; /* 0x1E8 Write Protect Status */ 69 u32 resg45_1[10]; 70 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 71 u32 res60_1[3]; 72 u32 csa; 73 u32 res60_2[56]; 74 #elif defined(CONFIG_AT91SAM9263) 75 u32 res63_1; 76 u32 tcmr; 77 u32 res63_2[2]; 78 u32 csa[2]; 79 u32 res63_3[54]; 80 #else 81 u32 reserve5[60]; 82 #endif 83 #endif 84 } at91_matrix_t; 85 86 #endif /* __ASSEMBLY__ */ 87 88 #define AT91_MATRIX_CSA_DBPUC 0x00000100 89 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 90 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 91 92 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 93 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 94 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 95 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 96 97 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 98 99 #if defined CONFIG_AT91SAM9261 100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 101 #define AT91_MATRIX_MCFG_RCB0 (1 << 0) 102 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 103 #define AT91_MATRIX_MCFG_RCB1 (1 << 1) 104 #endif 105 106 /* Undefined Length Burst Type */ 107 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 108 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 109 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 110 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 111 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 112 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 113 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 114 #endif 115 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 116 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 117 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 118 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007 119 #endif 120 121 /* Default Master Type */ 122 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 123 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 124 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 125 126 /* Fixed Index of Default Master */ 127 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \ 128 defined(CONFIG_AT91SAM9M10G45) 129 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) 130 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) 131 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) 132 #endif 133 134 /* Maximum Number of Allowed Cycles for a Burst */ 135 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 136 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) 137 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 138 defined(CONFIG_AT91SAM9263) 139 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) 140 #endif 141 142 /* Arbitration Type */ 143 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) 144 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 145 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 146 #endif 147 148 /* Master Remap Control Register */ 149 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 150 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 152 #define AT91_MATRIX_MRCR_RCB0 (1 << 0) 153 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 154 #define AT91_MATRIX_MRCR_RCB1 (1 << 1) 155 #endif 156 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \ 157 defined(CONFIG_AT91SAM9M10G45) 158 #define AT91_MATRIX_MRCR_RCB2 0x00000004 159 #define AT91_MATRIX_MRCR_RCB3 0x00000008 160 #define AT91_MATRIX_MRCR_RCB4 0x00000010 161 #define AT91_MATRIX_MRCR_RCB5 0x00000020 162 #define AT91_MATRIX_MRCR_RCB6 0x00000040 163 #define AT91_MATRIX_MRCR_RCB7 0x00000080 164 #define AT91_MATRIX_MRCR_RCB8 0x00000100 165 #endif 166 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 167 #define AT91_MATRIX_MRCR_RCB9 0x00000200 168 #define AT91_MATRIX_MRCR_RCB10 0x00000400 169 #define AT91_MATRIX_MRCR_RCB11 0x00000800 170 #endif 171 172 /* TCM Configuration Register */ 173 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 174 /* Size of ITCM enabled memory block */ 175 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 176 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040 177 /* Size of DTCM enabled memory block */ 178 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 179 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 180 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 181 /* Wait state TCM register */ 182 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 183 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 184 #endif 185 #if defined(CONFIG_AT91SAM9263) 186 /* Size of ITCM enabled memory block */ 187 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 188 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 189 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 190 /* Size of DTCM enabled memory block */ 191 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 192 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 193 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 194 #endif 195 #if defined(CONFIG_AT91SAM9261) 196 /* Size of ITCM enabled memory block */ 197 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 198 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 199 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 200 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007 201 /* Size of DTCM enabled memory block */ 202 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 203 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 204 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 205 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 206 #endif 207 208 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) 209 /* Video Mode Configuration Register */ 210 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 211 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 212 /* Write Protect Mode Register */ 213 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 214 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 215 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ 216 /* Write Protect Status Register */ 217 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000 218 #define AT91_MATRIX_WPSR_WPV 0x00000001 219 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ 220 #endif 221 222 /* USB Pad Pull-Up Control Register */ 223 #if defined(CONFIG_AT91SAM9261) 224 #define AT91_MATRIX_USBPUCR_PUON 0x40000000 225 #endif 226 227 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ 228 #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ 229 #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ 230 #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ 231 #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ 232 #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ 233 #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ 234 #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ 235 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ 236 #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ 237 #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ 238 239 #endif 240