1 /* 2 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef AT91_MATRIX_H 8 #define AT91_MATRIX_H 9 10 #ifdef __ASSEMBLY__ 11 12 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 13 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C) 14 #elif defined(CONFIG_AT91SAM9261) 15 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30) 16 #elif defined(CONFIG_AT91SAM9263) 17 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120) 18 #elif defined(CONFIG_AT91SAM9G45) 19 #define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128) 20 #else 21 #error AT91_ASM_MATRIX_CSA0 is not definied for current CPU 22 #endif 23 24 #define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX 25 26 #else 27 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 28 #define AT91_MATRIX_MASTERS 6 29 #define AT91_MATRIX_SLAVES 5 30 #elif defined(CONFIG_AT91SAM9261) 31 #define AT91_MATRIX_MASTERS 1 32 #define AT91_MATRIX_SLAVES 5 33 #elif defined(CONFIG_AT91SAM9263) 34 #define AT91_MATRIX_MASTERS 9 35 #define AT91_MATRIX_SLAVES 7 36 #elif defined(CONFIG_AT91SAM9G45) 37 #define AT91_MATRIX_MASTERS 11 38 #define AT91_MATRIX_SLAVES 8 39 #else 40 #error CPU not supported. Please update at91_matrix.h 41 #endif 42 43 typedef struct at91_priority { 44 u32 a; 45 u32 b; 46 } at91_priority_t; 47 48 typedef struct at91_matrix { 49 u32 mcfg[AT91_MATRIX_MASTERS]; 50 #if defined(CONFIG_AT91SAM9261) 51 u32 scfg[AT91_MATRIX_SLAVES]; 52 u32 res61_1[3]; 53 u32 tcr; 54 u32 res61_2[2]; 55 u32 csa; 56 u32 pucr; 57 u32 res61_3[114]; 58 #else 59 u32 reserve1[16 - AT91_MATRIX_MASTERS]; 60 u32 scfg[AT91_MATRIX_SLAVES]; 61 u32 reserve2[16 - AT91_MATRIX_SLAVES]; 62 at91_priority_t pr[AT91_MATRIX_SLAVES]; 63 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)]; 64 u32 mrcr; /* 0x100 Master Remap Control */ 65 u32 reserve4[3]; 66 #if defined(CONFIG_AT91SAM9G45) 67 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ 68 u32 womr; /* 0x1E4 Write Protect Mode */ 69 u32 wpsr; /* 0x1E8 Write Protect Status */ 70 u32 resg45_1[10]; 71 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) 72 u32 res60_1[3]; 73 u32 csa; 74 u32 res60_2[56]; 75 #elif defined(CONFIG_AT91SAM9263) 76 u32 res63_1; 77 u32 tcmr; 78 u32 res63_2[2]; 79 u32 csa[2]; 80 u32 res63_3[54]; 81 #else 82 u32 reserve5[60]; 83 #endif 84 #endif 85 } at91_matrix_t; 86 87 #endif /* __ASSEMBLY__ */ 88 89 #define AT91_MATRIX_CSA_DBPUC 0x00000100 90 #define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000 91 #define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000 92 93 #define AT91_MATRIX_CSA_EBI_CS1A 0x00000002 94 #define AT91_MATRIX_CSA_EBI_CS3A 0x00000008 95 #define AT91_MATRIX_CSA_EBI_CS4A 0x00000010 96 #define AT91_MATRIX_CSA_EBI_CS5A 0x00000020 97 98 #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 99 100 #if defined CONFIG_AT91SAM9261 101 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 102 #define AT91_MATRIX_MCFG_RCB0 (1 << 0) 103 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 104 #define AT91_MATRIX_MCFG_RCB1 (1 << 1) 105 #endif 106 107 /* Undefined Length Burst Type */ 108 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 109 defined(CONFIG_AT91SAM9G45) 110 #define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 111 #define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 112 #define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 113 #define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 114 #define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 115 #endif 116 #if defined(CONFIG_AT91SAM9G45) 117 #define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 118 #define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 119 #define AT91_MATRIX_MCFG_ULBT_128 0x00000007 120 #endif 121 122 /* Default Master Type */ 123 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 124 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 125 #define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 126 127 /* Fixed Index of Default Master */ 128 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) 129 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) 130 #elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) 131 #define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) 132 #endif 133 134 /* Maximum Number of Allowed Cycles for a Burst */ 135 #if defined(CONFIG_AT91SAM9G45) 136 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) 137 #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ 138 defined(CONFIG_AT91SAM9263) 139 #define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) 140 #endif 141 142 /* Arbitration Type */ 143 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) 144 #define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 145 #define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 146 #endif 147 148 /* Master Remap Control Register */ 149 #if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 150 defined(CONFIG_AT91SAM9G45) 151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 152 #define AT91_MATRIX_MRCR_RCB0 (1 << 0) 153 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 154 #define AT91_MATRIX_MRCR_RCB1 (1 << 1) 155 #endif 156 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) 157 #define AT91_MATRIX_MRCR_RCB2 0x00000004 158 #define AT91_MATRIX_MRCR_RCB3 0x00000008 159 #define AT91_MATRIX_MRCR_RCB4 0x00000010 160 #define AT91_MATRIX_MRCR_RCB5 0x00000020 161 #define AT91_MATRIX_MRCR_RCB6 0x00000040 162 #define AT91_MATRIX_MRCR_RCB7 0x00000080 163 #define AT91_MATRIX_MRCR_RCB8 0x00000100 164 #endif 165 #if defined(CONFIG_AT91SAM9G45) 166 #define AT91_MATRIX_MRCR_RCB9 0x00000200 167 #define AT91_MATRIX_MRCR_RCB10 0x00000400 168 #define AT91_MATRIX_MRCR_RCB11 0x00000800 169 #endif 170 171 /* TCM Configuration Register */ 172 #if defined(CONFIG_AT91SAM9G45) 173 /* Size of ITCM enabled memory block */ 174 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 175 #define AT91_MATRIX_TCMR_ITCM_32 0x00000040 176 /* Size of DTCM enabled memory block */ 177 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 178 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 179 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 180 /* Wait state TCM register */ 181 #define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 182 #define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 183 #endif 184 #if defined(CONFIG_AT91SAM9263) 185 /* Size of ITCM enabled memory block */ 186 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 187 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 188 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 189 /* Size of DTCM enabled memory block */ 190 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 191 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 192 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 193 #endif 194 #if defined(CONFIG_AT91SAM9261) 195 /* Size of ITCM enabled memory block */ 196 #define AT91_MATRIX_TCMR_ITCM_0 0x00000000 197 #define AT91_MATRIX_TCMR_ITCM_16 0x00000005 198 #define AT91_MATRIX_TCMR_ITCM_32 0x00000006 199 #define AT91_MATRIX_TCMR_ITCM_64 0x00000007 200 /* Size of DTCM enabled memory block */ 201 #define AT91_MATRIX_TCMR_DTCM_0 0x00000000 202 #define AT91_MATRIX_TCMR_DTCM_16 0x00000050 203 #define AT91_MATRIX_TCMR_DTCM_32 0x00000060 204 #define AT91_MATRIX_TCMR_DTCM_64 0x00000070 205 #endif 206 207 #if defined(CONFIG_AT91SAM9G45) 208 /* Video Mode Configuration Register */ 209 #define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 210 #define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 211 /* Write Protect Mode Register */ 212 #define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 213 #define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 214 #define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ 215 /* Write Protect Status Register */ 216 #define AT91_MATRIX_WPSR_NO_WPV 0x00000000 217 #define AT91_MATRIX_WPSR_WPV 0x00000001 218 #define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ 219 #endif 220 221 /* USB Pad Pull-Up Control Register */ 222 #if defined(CONFIG_AT91SAM9261) 223 #define AT91_MATRIX_USBPUCR_PUON 0x40000000 224 #endif 225 226 #define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ 227 #define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ 228 #define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ 229 #define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ 230 #define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ 231 #define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ 232 #define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ 233 #define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ 234 #define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ 235 #define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ 236 #define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ 237 238 #endif 239