xref: /openbmc/u-boot/arch/arm/mach-at91/clock.c (revision 70341e2ed9a0ff98a777febb7b56dbcee4d885c4)
1 /*
2  * Copyright (C) 2015 Atmel Corporation
3  *		      Wenyou Yang <wenyou.yang@atmel.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/at91_pmc.h>
12 
13 void at91_periph_clk_enable(int id)
14 {
15 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
16 
17 #ifdef CPU_HAS_PCR
18 	u32 regval;
19 	u32 div_value;
20 
21 	if (id > AT91_PMC_PCR_PID_MASK)
22 		return;
23 
24 	writel(id, &pmc->pcr);
25 
26 	div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV;
27 
28 	regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value;
29 
30 	writel(regval, &pmc->pcr);
31 #else
32 	writel(0x01 << id, &pmc->pcer);
33 #endif
34 }
35 
36 void at91_periph_clk_disable(int id)
37 {
38 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
39 
40 #ifdef CPU_HAS_PCR
41 	u32 regval;
42 
43 	if (id > AT91_PMC_PCR_PID_MASK)
44 		return;
45 
46 	regval = AT91_PMC_PCR_CMD_WRITE | id;
47 
48 	writel(regval, &pmc->pcr);
49 #else
50 	writel(0x01 << id, &pmc->pcdr);
51 #endif
52 }
53 
54 void at91_system_clk_enable(int sys_clk)
55 {
56 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
57 
58 	writel(sys_clk, &pmc->scer);
59 }
60 
61 void at91_system_clk_disable(int sys_clk)
62 {
63 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
64 
65 	writel(sys_clk, &pmc->scdr);
66 }
67