1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2013 7 * Bo Shen <voice.shen@atmel.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/at91_pit.h> 16 #include <asm/arch/clk.h> 17 #include <div64.h> 18 19 #if !defined(CONFIG_AT91FAMILY) 20 # error You need to define CONFIG_AT91FAMILY in your board config! 21 #endif 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 /* 26 * We're using the SAMA5D3x PITC in 32 bit mode, by 27 * setting the 20 bit counter period to its maximum (0xfffff). 28 * (See the relevant data sheets to understand that this really works) 29 * 30 * We do also mimic the typical powerpc way of incrementing 31 * two 32 bit registers called tbl and tbu. 32 * 33 * Those registers increment at 1/16 the main clock rate. 34 */ 35 36 #define TIMER_LOAD_VAL 0xfffff 37 38 /* 39 * Use the PITC in full 32 bit incrementing mode 40 */ 41 int timer_init(void) 42 { 43 at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; 44 45 /* Enable PITC Clock */ 46 at91_periph_clk_enable(ATMEL_ID_PIT); 47 48 /* Enable PITC */ 49 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); 50 51 gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; 52 53 return 0; 54 } 55 56 /* 57 * Return the number of timer ticks per second. 58 */ 59 ulong get_tbclk(void) 60 { 61 return gd->arch.timer_rate_hz; 62 } 63