1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * (C) Copyright 2013 7 * Bo Shen <voice.shen@atmel.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/arch/at91_pit.h> 16 #include <asm/arch/at91_pmc.h> 17 #include <asm/arch/clk.h> 18 #include <div64.h> 19 20 #if !defined(CONFIG_AT91FAMILY) 21 # error You need to define CONFIG_AT91FAMILY in your board config! 22 #endif 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* 27 * We're using the SAMA5D3x PITC in 32 bit mode, by 28 * setting the 20 bit counter period to its maximum (0xfffff). 29 * (See the relevant data sheets to understand that this really works) 30 * 31 * We do also mimic the typical powerpc way of incrementing 32 * two 32 bit registers called tbl and tbu. 33 * 34 * Those registers increment at 1/16 the main clock rate. 35 */ 36 37 #define TIMER_LOAD_VAL 0xfffff 38 39 /* 40 * Use the PITC in full 32 bit incrementing mode 41 */ 42 int timer_init(void) 43 { 44 at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; 45 46 /* Enable PITC Clock */ 47 at91_periph_clk_enable(ATMEL_ID_PIT); 48 49 /* Enable PITC */ 50 writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); 51 52 gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; 53 54 return 0; 55 } 56 57 /* 58 * Return the number of timer ticks per second. 59 */ 60 ulong get_tbclk(void) 61 { 62 return gd->arch.timer_rate_hz; 63 } 64