1*62011840SMasahiro Yamada /* 2*62011840SMasahiro Yamada * Copyright (C) 2014 Atmel 3*62011840SMasahiro Yamada * Bo Shen <voice.shen@atmel.com> 4*62011840SMasahiro Yamada * 5*62011840SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 6*62011840SMasahiro Yamada */ 7*62011840SMasahiro Yamada 8*62011840SMasahiro Yamada #include <common.h> 9*62011840SMasahiro Yamada #include <asm/io.h> 10*62011840SMasahiro Yamada #include <asm/arch/at91_common.h> 11*62011840SMasahiro Yamada #include <asm/arch/at91_pmc.h> 12*62011840SMasahiro Yamada #include <asm/arch/clk.h> 13*62011840SMasahiro Yamada #include <asm/arch/sama5_matrix.h> 14*62011840SMasahiro Yamada #include <asm/arch/sama5_sfr.h> 15*62011840SMasahiro Yamada #include <asm/arch/sama5d4.h> 16*62011840SMasahiro Yamada 17*62011840SMasahiro Yamada char *get_cpu_name() 18*62011840SMasahiro Yamada { 19*62011840SMasahiro Yamada unsigned int extension_id = get_extension_chip_id(); 20*62011840SMasahiro Yamada 21*62011840SMasahiro Yamada if (cpu_is_sama5d4()) 22*62011840SMasahiro Yamada switch (extension_id) { 23*62011840SMasahiro Yamada case ARCH_EXID_SAMA5D41: 24*62011840SMasahiro Yamada return "SAMA5D41"; 25*62011840SMasahiro Yamada case ARCH_EXID_SAMA5D42: 26*62011840SMasahiro Yamada return "SAMA5D42"; 27*62011840SMasahiro Yamada case ARCH_EXID_SAMA5D43: 28*62011840SMasahiro Yamada return "SAMA5D43"; 29*62011840SMasahiro Yamada case ARCH_EXID_SAMA5D44: 30*62011840SMasahiro Yamada return "SAMA5D44"; 31*62011840SMasahiro Yamada default: 32*62011840SMasahiro Yamada return "Unknown CPU type"; 33*62011840SMasahiro Yamada } 34*62011840SMasahiro Yamada else 35*62011840SMasahiro Yamada return "Unknown CPU type"; 36*62011840SMasahiro Yamada } 37*62011840SMasahiro Yamada 38*62011840SMasahiro Yamada #ifdef CONFIG_USB_GADGET_ATMEL_USBA 39*62011840SMasahiro Yamada void at91_udp_hw_init(void) 40*62011840SMasahiro Yamada { 41*62011840SMasahiro Yamada struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 42*62011840SMasahiro Yamada 43*62011840SMasahiro Yamada /* Enable UPLL clock */ 44*62011840SMasahiro Yamada writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); 45*62011840SMasahiro Yamada /* Enable UDPHS clock */ 46*62011840SMasahiro Yamada at91_periph_clk_enable(ATMEL_ID_UDPHS); 47*62011840SMasahiro Yamada } 48*62011840SMasahiro Yamada #endif 49*62011840SMasahiro Yamada 50*62011840SMasahiro Yamada #ifdef CONFIG_SPL_BUILD 51*62011840SMasahiro Yamada void matrix_init(void) 52*62011840SMasahiro Yamada { 53*62011840SMasahiro Yamada struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0; 54*62011840SMasahiro Yamada struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1; 55*62011840SMasahiro Yamada int i; 56*62011840SMasahiro Yamada 57*62011840SMasahiro Yamada /* Disable the write protect */ 58*62011840SMasahiro Yamada writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); 59*62011840SMasahiro Yamada writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); 60*62011840SMasahiro Yamada 61*62011840SMasahiro Yamada /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */ 62*62011840SMasahiro Yamada for (i = 4; i <= 10; i++) { 63*62011840SMasahiro Yamada writel(0x000f0f0f, &h64mx->ssr[i]); 64*62011840SMasahiro Yamada writel(0x0000ffff, &h64mx->sassr[i]); 65*62011840SMasahiro Yamada writel(0x0000000f, &h64mx->srtsr[i]); 66*62011840SMasahiro Yamada } 67*62011840SMasahiro Yamada 68*62011840SMasahiro Yamada /* CS3 */ 69*62011840SMasahiro Yamada writel(0x00c0c0c0, &h32mx->ssr[3]); 70*62011840SMasahiro Yamada writel(0xff000000, &h32mx->sassr[3]); 71*62011840SMasahiro Yamada writel(0xff000000, &h32mx->srtsr[3]); 72*62011840SMasahiro Yamada 73*62011840SMasahiro Yamada /* NFC SRAM */ 74*62011840SMasahiro Yamada writel(0x00010101, &h32mx->ssr[4]); 75*62011840SMasahiro Yamada writel(0x00000001, &h32mx->sassr[4]); 76*62011840SMasahiro Yamada writel(0x00000001, &h32mx->srtsr[4]); 77*62011840SMasahiro Yamada 78*62011840SMasahiro Yamada /* Enable the write protect */ 79*62011840SMasahiro Yamada writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); 80*62011840SMasahiro Yamada writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); 81*62011840SMasahiro Yamada } 82*62011840SMasahiro Yamada 83*62011840SMasahiro Yamada void redirect_int_from_saic_to_aic(void) 84*62011840SMasahiro Yamada { 85*62011840SMasahiro Yamada struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; 86*62011840SMasahiro Yamada u32 key32; 87*62011840SMasahiro Yamada 88*62011840SMasahiro Yamada if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) { 89*62011840SMasahiro Yamada key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY; 90*62011840SMasahiro Yamada writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); 91*62011840SMasahiro Yamada } 92*62011840SMasahiro Yamada } 93*62011840SMasahiro Yamada #endif 94