1/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
9 *
10 * SPDX-License-Identifier:	GPL-2.0+
11 */
12
13#include <config.h>
14#include <asm/arch/hardware.h>
15#include <asm/arch/at91_pmc.h>
16#include <asm/arch/at91_wdt.h>
17#include <asm/arch/at91_pio.h>
18#include <asm/arch/at91_matrix.h>
19#include <asm/arch/at91sam9_sdramc.h>
20#include <asm/arch/at91sam9_smc.h>
21#include <asm/arch/at91_rstc.h>
22#ifdef CONFIG_ATMEL_LEGACY
23#include <asm/arch/at91sam9_matrix.h>
24#endif
25#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
26#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
27#endif
28
29.globl lowlevel_init
30.type lowlevel_init,function
31lowlevel_init:
32
33POS1:
34	adr	r5, POS1	/* r5 = POS1 run time */
35	ldr	r0, =POS1	/* r0 = POS1 compile */
36	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
37
38	/* memory control configuration 1 */
39	ldr	r0, =SMRDATA
40	ldr	r2, =SMRDATA1
41	add	r0, r0, r5
42	add	r2, r2, r5
430:
44	/* the address */
45	ldr	r1, [r0], #4
46	/* the value */
47	ldr	r3, [r0], #4
48	str	r3, [r1]
49	cmp	r2, r0
50	bne	0b
51
52/* ----------------------------------------------------------------------------
53 * PMC Init Step 1.
54 * ----------------------------------------------------------------------------
55 * - Check if the PLL is already initialized
56 * ----------------------------------------------------------------------------
57 */
58	ldr	r1, =(AT91_ASM_PMC_MCKR)
59	ldr	r0, [r1]
60	and	r0, r0, #3
61	cmp	r0, #0
62	bne	PLL_setup_end
63
64/* ---------------------------------------------------------------------------
65 * - Enable the Main Oscillator
66 * ---------------------------------------------------------------------------
67 */
68	ldr	r1, =(AT91_ASM_PMC_MOR)
69	ldr	r2, =(AT91_ASM_PMC_SR)
70	/* Main oscillator Enable register PMC_MOR: */
71	ldr	r0, =CONFIG_SYS_MOR_VAL
72	str	r0, [r1]
73
74	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
75	mov	r4, #AT91_PMC_IXR_MOSCS
76MOSCS_Loop:
77	ldr	r3, [r2]
78	and	r3, r4, r3
79	cmp	r3, #AT91_PMC_IXR_MOSCS
80	bne	MOSCS_Loop
81
82/* ----------------------------------------------------------------------------
83 * PMC Init Step 2.
84 * ----------------------------------------------------------------------------
85 * Setup PLLA
86 * ----------------------------------------------------------------------------
87 */
88	ldr	r1, =(AT91_ASM_PMC_PLLAR)
89	ldr	r0, =CONFIG_SYS_PLLAR_VAL
90	str	r0, [r1]
91
92	/* Reading the PMC Status register to detect when the PLLA is locked */
93	mov	r4, #AT91_PMC_IXR_LOCKA
94MOSCS_Loop1:
95	ldr	r3, [r2]
96	and	r3, r4, r3
97	cmp	r3, #AT91_PMC_IXR_LOCKA
98	bne	MOSCS_Loop1
99
100/* ----------------------------------------------------------------------------
101 * PMC Init Step 3.
102 * ----------------------------------------------------------------------------
103 * - Switch on the Main Oscillator
104 * ----------------------------------------------------------------------------
105 */
106	ldr	r1, =(AT91_ASM_PMC_MCKR)
107
108	/* -Master Clock Controller register PMC_MCKR */
109	ldr	r0, =CONFIG_SYS_MCKR1_VAL
110	str	r0, [r1]
111
112	/* Reading the PMC Status to detect when the Master clock is ready */
113	mov	r4, #AT91_PMC_IXR_MCKRDY
114MCKRDY_Loop:
115	ldr	r3, [r2]
116	and	r3, r4, r3
117	cmp	r3, #AT91_PMC_IXR_MCKRDY
118	bne	MCKRDY_Loop
119
120	ldr	r0, =CONFIG_SYS_MCKR2_VAL
121	str	r0, [r1]
122
123	/* Reading the PMC Status to detect when the Master clock is ready */
124	mov	r4, #AT91_PMC_IXR_MCKRDY
125MCKRDY_Loop1:
126	ldr	r3, [r2]
127	and	r3, r4, r3
128	cmp	r3, #AT91_PMC_IXR_MCKRDY
129	bne	MCKRDY_Loop1
130PLL_setup_end:
131
132/* ----------------------------------------------------------------------------
133 * - memory control configuration 2
134 * ----------------------------------------------------------------------------
135 */
136	ldr	r0, =(AT91_ASM_SDRAMC_TR)
137	ldr	r1, [r0]
138	cmp	r1, #0
139	bne	SDRAM_setup_end
140
141	ldr	r0, =SMRDATA1
142	ldr	r2, =SMRDATA2
143	add	r0, r0, r5
144	add	r2, r2, r5
1452:
146	/* the address */
147	ldr	r1, [r0], #4
148	/* the value */
149	ldr	r3, [r0], #4
150	str	r3, [r1]
151	cmp	r2, r0
152	bne	2b
153
154SDRAM_setup_end:
155	/* everything is fine now */
156	mov	pc, lr
157
158	.ltorg
159
160SMRDATA:
161	.word AT91_ASM_WDT_MR
162	.word CONFIG_SYS_WDTC_WDMR_VAL
163	/* configure PIOx as EBI0 D[16-31] */
164#if defined(CONFIG_AT91SAM9263)
165	.word AT91_ASM_PIOD_PDR
166	.word CONFIG_SYS_PIOD_PDR_VAL1
167	.word AT91_ASM_PIOD_PUDR
168	.word CONFIG_SYS_PIOD_PPUDR_VAL
169	.word AT91_ASM_PIOD_ASR
170	.word CONFIG_SYS_PIOD_PPUDR_VAL
171#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
172	|| defined(CONFIG_AT91SAM9G20)
173	.word AT91_ASM_PIOC_PDR
174	.word CONFIG_SYS_PIOC_PDR_VAL1
175	.word AT91_ASM_PIOC_PUDR
176	.word CONFIG_SYS_PIOC_PPUDR_VAL
177#endif
178	.word AT91_ASM_MATRIX_CSA0
179	.word CONFIG_SYS_MATRIX_EBICSA_VAL
180
181	/* flash */
182	.word AT91_ASM_SMC_MODE0
183	.word CONFIG_SYS_SMC0_MODE0_VAL
184
185	.word AT91_ASM_SMC_CYCLE0
186	.word CONFIG_SYS_SMC0_CYCLE0_VAL
187
188	.word AT91_ASM_SMC_PULSE0
189	.word CONFIG_SYS_SMC0_PULSE0_VAL
190
191	.word AT91_ASM_SMC_SETUP0
192	.word CONFIG_SYS_SMC0_SETUP0_VAL
193
194SMRDATA1:
195	.word AT91_ASM_SDRAMC_MR
196	.word CONFIG_SYS_SDRC_MR_VAL1
197	.word AT91_ASM_SDRAMC_TR
198	.word CONFIG_SYS_SDRC_TR_VAL1
199	.word AT91_ASM_SDRAMC_CR
200	.word CONFIG_SYS_SDRC_CR_VAL
201	.word AT91_ASM_SDRAMC_MDR
202	.word CONFIG_SYS_SDRC_MDR_VAL
203	.word AT91_ASM_SDRAMC_MR
204	.word CONFIG_SYS_SDRC_MR_VAL2
205	.word CONFIG_SYS_SDRAM_BASE
206	.word CONFIG_SYS_SDRAM_VAL1
207	.word AT91_ASM_SDRAMC_MR
208	.word CONFIG_SYS_SDRC_MR_VAL3
209	.word CONFIG_SYS_SDRAM_BASE
210	.word CONFIG_SYS_SDRAM_VAL2
211	.word CONFIG_SYS_SDRAM_BASE
212	.word CONFIG_SYS_SDRAM_VAL3
213	.word CONFIG_SYS_SDRAM_BASE
214	.word CONFIG_SYS_SDRAM_VAL4
215	.word CONFIG_SYS_SDRAM_BASE
216	.word CONFIG_SYS_SDRAM_VAL5
217	.word CONFIG_SYS_SDRAM_BASE
218	.word CONFIG_SYS_SDRAM_VAL6
219	.word CONFIG_SYS_SDRAM_BASE
220	.word CONFIG_SYS_SDRAM_VAL7
221	.word CONFIG_SYS_SDRAM_BASE
222	.word CONFIG_SYS_SDRAM_VAL8
223	.word CONFIG_SYS_SDRAM_BASE
224	.word CONFIG_SYS_SDRAM_VAL9
225	.word AT91_ASM_SDRAMC_MR
226	.word CONFIG_SYS_SDRC_MR_VAL4
227	.word CONFIG_SYS_SDRAM_BASE
228	.word CONFIG_SYS_SDRAM_VAL10
229	.word AT91_ASM_SDRAMC_MR
230	.word CONFIG_SYS_SDRC_MR_VAL5
231	.word CONFIG_SYS_SDRAM_BASE
232	.word CONFIG_SYS_SDRAM_VAL11
233	.word AT91_ASM_SDRAMC_TR
234	.word CONFIG_SYS_SDRC_TR_VAL2
235	.word CONFIG_SYS_SDRAM_BASE
236	.word CONFIG_SYS_SDRAM_VAL12
237	/* User reset enable*/
238	.word AT91_ASM_RSTC_MR
239	.word CONFIG_SYS_RSTC_RMR_VAL
240#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
241	/* MATRIX_MCFG - REMAP all masters */
242	.word AT91_ASM_MATRIX_MCFG
243	.word 0x1FF
244#endif
245SMRDATA2:
246	.word 0
247