1 /* 2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] 3 * 4 * Copyright (C) 2005 David Brownell 5 * Copyright (C) 2005 Ivan Kokshaysky 6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/at91_pmc.h> 15 #include <asm/arch/clk.h> 16 17 #if !defined(CONFIG_AT91FAMILY) 18 # error You need to define CONFIG_AT91FAMILY in your board config! 19 #endif 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 static unsigned long at91_css_to_rate(unsigned long css) 24 { 25 switch (css) { 26 case AT91_PMC_MCKR_CSS_SLOW: 27 return CONFIG_SYS_AT91_SLOW_CLOCK; 28 case AT91_PMC_MCKR_CSS_MAIN: 29 return gd->arch.main_clk_rate_hz; 30 case AT91_PMC_MCKR_CSS_PLLA: 31 return gd->arch.plla_rate_hz; 32 case AT91_PMC_MCKR_CSS_PLLB: 33 return gd->arch.pllb_rate_hz; 34 } 35 36 return 0; 37 } 38 39 #ifdef CONFIG_USB_ATMEL 40 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) 41 { 42 unsigned i, div = 0, mul = 0, diff = 1 << 30; 43 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; 44 45 /* PLL output max 240 MHz (or 180 MHz per errata) */ 46 if (out_freq > 240000000) 47 goto fail; 48 49 for (i = 1; i < 256; i++) { 50 int diff1; 51 unsigned input, mul1; 52 53 /* 54 * PLL input between 1MHz and 32MHz per spec, but lower 55 * frequences seem necessary in some cases so allow 100K. 56 * Warning: some newer products need 2MHz min. 57 */ 58 input = main_freq / i; 59 #if defined(CONFIG_AT91SAM9G20) 60 if (input < 2000000) 61 continue; 62 #endif 63 if (input < 100000) 64 continue; 65 if (input > 32000000) 66 continue; 67 68 mul1 = out_freq / input; 69 #if defined(CONFIG_AT91SAM9G20) 70 if (mul > 63) 71 continue; 72 #endif 73 if (mul1 > 2048) 74 continue; 75 if (mul1 < 2) 76 goto fail; 77 78 diff1 = out_freq - input * mul1; 79 if (diff1 < 0) 80 diff1 = -diff1; 81 if (diff > diff1) { 82 diff = diff1; 83 div = i; 84 mul = mul1; 85 if (diff == 0) 86 break; 87 } 88 } 89 if (i == 256 && diff > (out_freq >> 5)) 90 goto fail; 91 return ret | ((mul - 1) << 16) | div; 92 fail: 93 return 0; 94 } 95 #endif 96 97 static u32 at91_pll_rate(u32 freq, u32 reg) 98 { 99 unsigned mul, div; 100 101 div = reg & 0xff; 102 mul = (reg >> 16) & 0x7ff; 103 if (div && mul) { 104 freq /= div; 105 freq *= mul + 1; 106 } else 107 freq = 0; 108 109 return freq; 110 } 111 112 int at91_clock_init(unsigned long main_clock) 113 { 114 unsigned freq, mckr; 115 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 116 #ifndef CONFIG_SYS_AT91_MAIN_CLOCK 117 unsigned tmp; 118 /* 119 * When the bootloader initialized the main oscillator correctly, 120 * there's no problem using the cycle counter. But if it didn't, 121 * or when using oscillator bypass mode, we must be told the speed 122 * of the main clock. 123 */ 124 if (!main_clock) { 125 do { 126 tmp = readl(&pmc->mcfr); 127 } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); 128 tmp &= AT91_PMC_MCFR_MAINF_MASK; 129 main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); 130 } 131 #endif 132 gd->arch.main_clk_rate_hz = main_clock; 133 134 /* report if PLLA is more than mildly overclocked */ 135 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); 136 137 #ifdef CONFIG_USB_ATMEL 138 /* 139 * USB clock init: choose 48 MHz PLLB value, 140 * disable 48MHz clock during usb peripheral suspend. 141 * 142 * REVISIT: assumes MCK doesn't derive from PLLB! 143 */ 144 gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | 145 AT91_PMC_PLLBR_USBDIV_2; 146 gd->arch.pllb_rate_hz = at91_pll_rate(main_clock, 147 gd->arch.at91_pllb_usb_init); 148 #endif 149 150 /* 151 * MCK and CPU derive from one of those primary clocks. 152 * For now, assume this parentage won't change. 153 */ 154 mckr = readl(&pmc->mckr); 155 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ 156 || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) 157 /* plla divisor by 2 */ 158 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); 159 #endif 160 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); 161 freq = gd->arch.mck_rate_hz; 162 163 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ 164 #if defined(CONFIG_AT91SAM9G20) 165 /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ 166 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? 167 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; 168 if (mckr & AT91_PMC_MCKR_MDIV_MASK) 169 freq /= 2; /* processor clock division */ 170 #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ 171 || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) 172 /* mdiv <==> divisor 173 * 0 <==> 1 174 * 1 <==> 2 175 * 2 <==> 4 176 * 3 <==> 3 177 */ 178 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == 179 (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) 180 ? freq / 3 181 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); 182 #else 183 gd->arch.mck_rate_hz = freq / 184 (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); 185 #endif 186 gd->arch.cpu_clk_rate_hz = freq; 187 188 return 0; 189 } 190 191 #if !defined(AT91_PLL_LOCK_TIMEOUT) 192 #define AT91_PLL_LOCK_TIMEOUT 1000000 193 #endif 194 195 void at91_plla_init(u32 pllar) 196 { 197 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 198 int timeout = AT91_PLL_LOCK_TIMEOUT; 199 200 writel(pllar, &pmc->pllar); 201 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { 202 timeout--; 203 if (timeout == 0) 204 break; 205 } 206 } 207 void at91_pllb_init(u32 pllbr) 208 { 209 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 210 int timeout = AT91_PLL_LOCK_TIMEOUT; 211 212 writel(pllbr, &pmc->pllbr); 213 while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { 214 timeout--; 215 if (timeout == 0) 216 break; 217 } 218 } 219 220 void at91_mck_init(u32 mckr) 221 { 222 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 223 int timeout = AT91_PLL_LOCK_TIMEOUT; 224 u32 tmp; 225 226 tmp = readl(&pmc->mckr); 227 tmp &= ~(AT91_PMC_MCKR_PRES_MASK | 228 AT91_PMC_MCKR_MDIV_MASK | 229 AT91_PMC_MCKR_PLLADIV_MASK | 230 AT91_PMC_MCKR_CSS_MASK); 231 tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | 232 AT91_PMC_MCKR_MDIV_MASK | 233 AT91_PMC_MCKR_PLLADIV_MASK | 234 AT91_PMC_MCKR_CSS_MASK); 235 writel(tmp, &pmc->mckr); 236 237 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { 238 timeout--; 239 if (timeout == 0) 240 break; 241 } 242 } 243 244 void at91_periph_clk_enable(int id) 245 { 246 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 247 248 writel(1 << id, &pmc->pcer); 249 } 250