1 /* 2 * Copyright (C) 2012 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/at91_common.h> 9 #include <asm/arch/at91_pmc.h> 10 #include <asm/arch/gpio.h> 11 #include <asm/io.h> 12 13 unsigned int get_chip_id(void) 14 { 15 /* The 0x40 is the offset of cidr in DBGU */ 16 return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; 17 } 18 19 unsigned int get_extension_chip_id(void) 20 { 21 /* The 0x44 is the offset of exid in DBGU */ 22 return readl(ATMEL_BASE_DBGU + 0x44); 23 } 24 25 unsigned int has_emac1() 26 { 27 return cpu_is_at91sam9x25(); 28 } 29 30 unsigned int has_emac0() 31 { 32 return !(cpu_is_at91sam9g15()); 33 } 34 35 unsigned int has_lcdc() 36 { 37 return cpu_is_at91sam9g15() || cpu_is_at91sam9g35() 38 || cpu_is_at91sam9x35(); 39 } 40 41 char *get_cpu_name() 42 { 43 unsigned int extension_id = get_extension_chip_id(); 44 45 if (cpu_is_at91sam9x5()) { 46 switch (extension_id) { 47 case ARCH_EXID_AT91SAM9G15: 48 return "AT91SAM9G15"; 49 case ARCH_EXID_AT91SAM9G25: 50 return "AT91SAM9G25"; 51 case ARCH_EXID_AT91SAM9G35: 52 return "AT91SAM9G35"; 53 case ARCH_EXID_AT91SAM9X25: 54 return "AT91SAM9X25"; 55 case ARCH_EXID_AT91SAM9X35: 56 return "AT91SAM9X35"; 57 default: 58 return "Unknown CPU type"; 59 } 60 } else { 61 return "Unknown CPU type"; 62 } 63 } 64 65 void at91_seriald_hw_init(void) 66 { 67 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 68 69 at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ 70 at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ 71 72 writel(1 << ATMEL_ID_SYS, &pmc->pcer); 73 } 74 75 void at91_serial0_hw_init(void) 76 { 77 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 78 79 at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ 80 at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ 81 82 writel(1 << ATMEL_ID_USART0, &pmc->pcer); 83 } 84 85 void at91_serial1_hw_init(void) 86 { 87 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 88 89 at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ 90 at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ 91 92 writel(1 << ATMEL_ID_USART1, &pmc->pcer); 93 } 94 95 void at91_serial2_hw_init(void) 96 { 97 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 98 99 at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ 100 at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ 101 102 writel(1 << ATMEL_ID_USART2, &pmc->pcer); 103 } 104 105 void at91_mci_hw_init(void) 106 { 107 /* Initialize the MCI0 */ 108 at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ 109 at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ 110 at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ 111 at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ 112 at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ 113 at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ 114 115 /* Enable clock for MCI0 */ 116 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 117 writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); 118 } 119 120 #ifdef CONFIG_ATMEL_SPI 121 void at91_spi0_hw_init(unsigned long cs_mask) 122 { 123 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 124 125 at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ 126 at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ 127 at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ 128 129 /* Enable clock */ 130 writel(1 << ATMEL_ID_SPI0, &pmc->pcer); 131 132 if (cs_mask & (1 << 0)) 133 at91_set_a_periph(AT91_PIO_PORTA, 14, 0); 134 if (cs_mask & (1 << 1)) 135 at91_set_b_periph(AT91_PIO_PORTA, 7, 0); 136 if (cs_mask & (1 << 2)) 137 at91_set_b_periph(AT91_PIO_PORTA, 1, 0); 138 if (cs_mask & (1 << 3)) 139 at91_set_b_periph(AT91_PIO_PORTB, 3, 0); 140 if (cs_mask & (1 << 4)) 141 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 142 if (cs_mask & (1 << 5)) 143 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 144 if (cs_mask & (1 << 6)) 145 at91_set_pio_output(AT91_PIO_PORTA, 1, 0); 146 if (cs_mask & (1 << 7)) 147 at91_set_pio_output(AT91_PIO_PORTB, 3, 0); 148 } 149 150 void at91_spi1_hw_init(unsigned long cs_mask) 151 { 152 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 153 154 at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ 155 at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ 156 at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ 157 158 /* Enable clock */ 159 writel(1 << ATMEL_ID_SPI1, &pmc->pcer); 160 161 if (cs_mask & (1 << 0)) 162 at91_set_b_periph(AT91_PIO_PORTA, 8, 0); 163 if (cs_mask & (1 << 1)) 164 at91_set_b_periph(AT91_PIO_PORTA, 0, 0); 165 if (cs_mask & (1 << 2)) 166 at91_set_b_periph(AT91_PIO_PORTA, 31, 0); 167 if (cs_mask & (1 << 3)) 168 at91_set_b_periph(AT91_PIO_PORTA, 30, 0); 169 if (cs_mask & (1 << 4)) 170 at91_set_pio_output(AT91_PIO_PORTA, 8, 0); 171 if (cs_mask & (1 << 5)) 172 at91_set_pio_output(AT91_PIO_PORTA, 0, 0); 173 if (cs_mask & (1 << 6)) 174 at91_set_pio_output(AT91_PIO_PORTA, 31, 0); 175 if (cs_mask & (1 << 7)) 176 at91_set_pio_output(AT91_PIO_PORTA, 30, 0); 177 } 178 #endif 179 180 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) 181 void at91_uhp_hw_init(void) 182 { 183 /* Enable VBus on UHP ports */ 184 at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ 185 at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ 186 #if defined(CONFIG_USB_OHCI_NEW) 187 /* port C is OHCI only */ 188 at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ 189 #endif 190 } 191 #endif 192 193 #ifdef CONFIG_MACB 194 void at91_macb_hw_init(void) 195 { 196 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; 197 198 if (has_emac0()) { 199 /* Enable EMAC0 clock */ 200 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); 201 /* EMAC0 pins setup */ 202 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ 203 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ 204 at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ 205 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ 206 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ 207 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ 208 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ 209 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ 210 at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ 211 at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ 212 } 213 214 if (has_emac1()) { 215 /* Enable EMAC1 clock */ 216 writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); 217 /* EMAC1 pins setup */ 218 at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ 219 at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ 220 at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ 221 at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ 222 at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ 223 at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ 224 at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ 225 at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ 226 at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ 227 at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ 228 } 229 230 #ifndef CONFIG_RMII 231 /* Only emac0 support MII */ 232 if (has_emac0()) { 233 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ 234 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ 235 at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ 236 at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ 237 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ 238 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ 239 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ 240 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ 241 } 242 #endif 243 } 244 #endif 245