1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <asm/io.h> 10 #include <asm/arch/aspeed_scu_info.h> 11 #include <asm/arch/platform.h> 12 13 #if defined(CONFIG_DISPLAY_CPUINFO) 14 /* SoC mapping Table */ 15 struct soc_id { 16 const char *name; 17 u32 rev_id; 18 }; 19 20 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, } 21 22 static struct soc_id soc_map_table[] = { 23 SOC_ID("AST1100/AST2050-A0", 0x00000200), 24 SOC_ID("AST1100/AST2050-A1", 0x00000201), 25 SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202), 26 SOC_ID("AST1510/AST2100-A0", 0x00000300), 27 SOC_ID("AST1510/AST2100-A1", 0x00000301), 28 SOC_ID("AST1510/AST2100-A2,3", 0x00000302), 29 SOC_ID("AST2200-A0,1", 0x00000102), 30 SOC_ID("AST2300-A0", 0x01000003), 31 SOC_ID("AST2300-A1", 0x01010303), 32 SOC_ID("AST1300-A1", 0x01010003), 33 SOC_ID("AST1050-A1", 0x01010203), 34 SOC_ID("AST2400-A0", 0x02000303), 35 SOC_ID("AST2400-A1", 0x02010303), 36 SOC_ID("AST1010-A0", 0x03000003), 37 SOC_ID("AST1010-A1", 0x03010003), 38 SOC_ID("AST3200-A0", 0x04002003), 39 SOC_ID("AST3200-A1", 0x04012003), 40 SOC_ID("AST3200-A2", 0x04032003), 41 SOC_ID("AST1520-A0", 0x03000203), 42 SOC_ID("AST1520-A1", 0x03010203), 43 SOC_ID("AST2510-A0", 0x04000103), 44 SOC_ID("AST2510-A1", 0x04010103), 45 SOC_ID("AST2510-A2", 0x04030103), 46 SOC_ID("AST2520-A0", 0x04000203), 47 SOC_ID("AST2520-A1", 0x04010203), 48 SOC_ID("AST2520-A2", 0x04030203), 49 SOC_ID("AST2500-A0", 0x04000303), 50 SOC_ID("AST2500-A1", 0x04010303), 51 SOC_ID("AST2500-A2", 0x04030303), 52 SOC_ID("AST2530-A0", 0x04000403), 53 SOC_ID("AST2530-A1", 0x04010403), 54 SOC_ID("AST2530-A2", 0x04030403), 55 SOC_ID("AST2600-A0", 0x05000303), 56 }; 57 58 void aspeed_get_revision_id(void) 59 { 60 int i; 61 u32 rev_id = readl(ASPEED_REVISION_ID); 62 for(i=0;i<ARRAY_SIZE(soc_map_table);i++) { 63 if(rev_id == soc_map_table[i].rev_id) 64 break; 65 } 66 if(i == ARRAY_SIZE(soc_map_table)) 67 printf("UnKnow-SOC : %x \n",rev_id); 68 else 69 printf("SOC : %4s \n",soc_map_table[i].name); 70 } 71 72 int print_cpuinfo(void) 73 { 74 int i = 0; 75 ulong size = 0; 76 77 aspeed_get_revision_id(); 78 aspeed_sys_reset_info(); 79 80 aspeed_security_info(); 81 82 #if 0 83 printf("PLL : %4s MHz\n", strmhz(buf, aspeed_get_clk_in_rate())); 84 85 printf("CPU : %4s MHz\n", strmhz(buf, aspeed_get_hpll_clk_rate())); 86 printf("MPLL : %4s MHz, ECC: %s, ", 87 strmhz(buf, aspeed_get_mpll_clk_rate()), 88 ast_sdmc_get_ecc() ? "Enable" : "Disable"); 89 90 if(ast_sdmc_get_ecc()) 91 printf("recover %d, un-recover %d, ", ast_sdmc_get_ecc_recover_count(), ast_sdmc_get_ecc_unrecover_count()); 92 if(ast_sdmc_get_ecc()) 93 printf("Size : %d MB, ", ast_sdmc_get_ecc_size()/1024/1024); 94 95 #if defined(CONFIG_MACH_ASPEED_G5) 96 printf("Cache: %s ",ast_sdmc_get_cache() ? "Enable" : "Disable"); 97 #endif 98 aspeed_who_init_dram(); 99 100 size = ast_sdmc_get_vram_size(); 101 102 puts("VGA : "); 103 print_size(size, "- "); 104 105 size = ast_sdmc_get_mem_size(); 106 puts("Total DRAM : "); 107 print_size(size, "\n"); 108 #endif 109 110 aspeed_2nd_wdt_mode(); 111 112 aspeed_spi_strap_mode(); 113 114 aspeed_espi_mode(); 115 116 puts("Eth : "); 117 for(i = 0; i < ASPEED_MAC_COUNT; i++) { 118 printf("MAC%d: %s ",i, aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI"); 119 if(i != (ASPEED_MAC_COUNT - 1)) 120 printf(","); 121 } 122 puts("\n"); 123 124 return 0; 125 } 126 #endif 127 128 #if defined(CONFIG_MACH_ASPEED_G6) 129 int arch_cpu_init(void) 130 { 131 //unlock 13 scu 132 writel(0x1688a8a8, 0x1e6e2010); 133 134 return 0; 135 } 136 #endif 137