1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 * Ryan Chen <ryan_chen@aspeedtech.com> 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <asm/io.h> 10 #include <asm/arch/aspeed_scu_info.h> 11 #include <asm/arch/platform.h> 12 #ifdef CONFIG_ASPEED_AST2500 13 #include <asm/arch/scu_ast2500.h> 14 #endif 15 #ifdef CONFIG_ASPEED_AST2600 16 #include <asm/arch/scu_ast2600.h> 17 #endif 18 19 #if defined(CONFIG_DISPLAY_CPUINFO) 20 /* SoC mapping Table */ 21 struct soc_id { 22 const char *name; 23 u32 rev_id; 24 }; 25 26 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, } 27 28 static struct soc_id soc_map_table[] = { 29 SOC_ID("AST1100/AST2050-A0", 0x00000200), 30 SOC_ID("AST1100/AST2050-A1", 0x00000201), 31 SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202), 32 SOC_ID("AST1510/AST2100-A0", 0x00000300), 33 SOC_ID("AST1510/AST2100-A1", 0x00000301), 34 SOC_ID("AST1510/AST2100-A2,3", 0x00000302), 35 SOC_ID("AST2200-A0,1", 0x00000102), 36 SOC_ID("AST2300-A0", 0x01000003), 37 SOC_ID("AST2300-A1", 0x01010303), 38 SOC_ID("AST1300-A1", 0x01010003), 39 SOC_ID("AST1050-A1", 0x01010203), 40 SOC_ID("AST2400-A0", 0x02000303), 41 SOC_ID("AST2400-A1", 0x02010303), 42 SOC_ID("AST1010-A0", 0x03000003), 43 SOC_ID("AST1010-A1", 0x03010003), 44 SOC_ID("AST3200-A0", 0x04002003), 45 SOC_ID("AST3200-A1", 0x04012003), 46 SOC_ID("AST3200-A2", 0x04032003), 47 SOC_ID("AST1520-A0", 0x03000203), 48 SOC_ID("AST1520-A1", 0x03010203), 49 SOC_ID("AST2510-A0", 0x04000103), 50 SOC_ID("AST2510-A1", 0x04010103), 51 SOC_ID("AST2510-A2", 0x04030103), 52 SOC_ID("AST2520-A0", 0x04000203), 53 SOC_ID("AST2520-A1", 0x04010203), 54 SOC_ID("AST2520-A2", 0x04030203), 55 SOC_ID("AST2500-A0", 0x04000303), 56 SOC_ID("AST2500-A1", 0x04010303), 57 SOC_ID("AST2500-A2", 0x04030303), 58 SOC_ID("AST2530-A0", 0x04000403), 59 SOC_ID("AST2530-A1", 0x04010403), 60 SOC_ID("AST2530-A2", 0x04030403), 61 SOC_ID("AST2600-A0", 0x05000303), 62 }; 63 64 void aspeed_get_revision_id(void) 65 { 66 int i; 67 u32 rev_id = readl(ASPEED_REVISION_ID); 68 for(i=0;i<ARRAY_SIZE(soc_map_table);i++) { 69 if(rev_id == soc_map_table[i].rev_id) 70 break; 71 } 72 if(i == ARRAY_SIZE(soc_map_table)) 73 printf("UnKnow-SOC : %x \n",rev_id); 74 else 75 printf("SOC : %4s \n",soc_map_table[i].name); 76 } 77 78 int print_cpuinfo(void) 79 { 80 char buf[32]; 81 int i = 0; 82 ulong size = 0; 83 84 aspeed_get_revision_id(); 85 aspeed_sys_reset_info(); 86 aspeed_security_info(); 87 88 #if 0 89 printf("PLL : %4s MHz\n", strmhz(buf, aspeed_get_clk_in_rate())); 90 91 printf("CPU : %4s MHz\n", strmhz(buf, aspeed_get_hpll_clk_rate())); 92 printf("MPLL : %4s MHz, ECC: %s, ", 93 strmhz(buf, aspeed_get_mpll_clk_rate()), 94 ast_sdmc_get_ecc() ? "Enable" : "Disable"); 95 96 if(ast_sdmc_get_ecc()) 97 printf("recover %d, un-recover %d, ", ast_sdmc_get_ecc_recover_count(), ast_sdmc_get_ecc_unrecover_count()); 98 if(ast_sdmc_get_ecc()) 99 printf("Size : %d MB, ", ast_sdmc_get_ecc_size()/1024/1024); 100 101 #if defined(CONFIG_MACH_ASPEED_G5) 102 printf("Cache: %s ",ast_sdmc_get_cache() ? "Enable" : "Disable"); 103 #endif 104 aspeed_who_init_dram(); 105 106 size = ast_sdmc_get_vram_size(); 107 108 puts("VGA : "); 109 print_size(size, "- "); 110 111 size = ast_sdmc_get_mem_size(); 112 puts("Total DRAM : "); 113 print_size(size, "\n"); 114 #endif 115 116 #if defined(CONFIG_ASPEED_AST2500) 117 struct ast2500_scu *scu = (struct ast2500_scu *)0x1e6e2000; 118 119 printf("PLL : %4s MHz\n", strmhz(buf, ast2500_get_clkin(scu))); 120 printf("HPLL : %4s MHz\n", strmhz(buf, ast2500_get_hpll_rate(scu))); 121 printf("MPLL : %4s Mhz\n", strmhz(buf, ast2500_get_mpll_rate(scu))); 122 printf("DPLL : %4s Mhz\n", strmhz(buf, ast2500_get_dpll_rate(scu))); 123 printf("D2PLL : %4s Mhz\n", strmhz(buf, ast2500_get_d2pll_rate(scu))); 124 #elif defined(CONFIG_ASPEED_AST2600) 125 struct ast2600_scu *scu = (struct ast2600_scu *)0x1e6e2000; 126 127 printf("PLL : %4s MHz\n", strmhz(buf, AST2600_CLK_IN)); 128 printf("HPLL : %4s MHz\n", strmhz(buf, ast2600_get_hpll_rate(scu))); 129 printf("MPLL : %4s Mhz\n", strmhz(buf, ast2600_get_mpll_rate(scu))); 130 printf("APLL : %4s Mhz\n", strmhz(buf, ast2600_get_apll_rate(scu))); 131 printf("EPLL : %4s Mhz\n", strmhz(buf, ast2600_get_epll_rate(scu))); 132 printf("DPLL : %4s Mhz\n", strmhz(buf, ast2600_get_dpll_rate(scu))); 133 #else 134 #endif 135 136 aspeed_2nd_wdt_mode(); 137 138 aspeed_spi_strap_mode(); 139 140 aspeed_espi_mode(); 141 142 puts("Eth : "); 143 for(i = 0; i < ASPEED_MAC_COUNT; i++) { 144 printf("MAC%d: %s ",i, aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI"); 145 if(i != (ASPEED_MAC_COUNT - 1)) 146 printf(","); 147 } 148 puts("\n"); 149 150 return 0; 151 } 152 #endif 153 154 #if defined(CONFIG_MACH_ASPEED_G6) 155 int arch_cpu_init(void) 156 { 157 //unlock 13 scu 158 writel(0x1688a8a8, 0x1e6e2010); 159 160 return 0; 161 } 162 #endif 163