1 /* 2 * (C) Copyright ASPEED Technology Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <debug_uart.h> 8 #include <spl.h> 9 #include <dm.h> 10 #include <mmc.h> 11 #include <xyzModem.h> 12 #include <asm/io.h> 13 #include <asm/arch/aspeed_verify.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #define AST_BOOTMODE_SPI 0 18 #define AST_BOOTMODE_EMMC 1 19 #define AST_BOOTMODE_UART 2 20 21 u32 aspeed_bootmode(void); 22 void aspeed_mmc_init(void); 23 static void spl_boot_from_uart_wdt_disable(void); 24 25 void board_init_f(ulong dummy) 26 { 27 #ifndef CONFIG_SPL_TINY 28 struct udevice *dev; 29 spl_early_init(); 30 timer_init(); 31 uclass_get_device(UCLASS_PINCTRL, 0, &dev); 32 preloader_console_init(); 33 dram_init(); 34 aspeed_mmc_init(); 35 spl_boot_from_uart_wdt_disable(); 36 #endif 37 } 38 39 #ifdef CONFIG_SPL_BOARD_INIT 40 void spl_board_init(void) 41 { 42 struct udevice *dev; 43 44 if (IS_ENABLED(CONFIG_ASPEED_HACE) && 45 uclass_get_device_by_driver(UCLASS_MISC, 46 DM_GET_DRIVER(aspeed_hace), 47 &dev)) { 48 debug("Warning: HACE initialization failure\n"); 49 } 50 } 51 #endif 52 53 u32 spl_boot_device(void) 54 { 55 switch (aspeed_bootmode()) { 56 case AST_BOOTMODE_EMMC: 57 return BOOT_DEVICE_MMC1; 58 case AST_BOOTMODE_SPI: 59 return BOOT_DEVICE_RAM; 60 case AST_BOOTMODE_UART: 61 return BOOT_DEVICE_UART; 62 default: 63 break; 64 } 65 66 return BOOT_DEVICE_NONE; 67 } 68 69 #ifdef CONFIG_SPL_OS_BOOT 70 int spl_start_uboot(void) 71 { 72 /* boot linux */ 73 return 0; 74 } 75 #endif 76 77 int board_fit_config_name_match(const char *name) 78 { 79 /* we always use the default configuration */ 80 debug("%s: %s\n", __func__, name); 81 return 0; 82 } 83 84 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) 85 { 86 return (struct image_header *)(CONFIG_SYS_LOAD_ADDR); 87 } 88 89 static void spl_boot_from_uart_wdt_disable(void) 90 { 91 int boot_mode = aspeed_bootmode(); 92 93 /* Disable ABR WDT for SPI flash and eMMC ABR. */ 94 if (boot_mode == AST_BOOTMODE_UART) { 95 writel(0, 0x1e620064); 96 writel(0, 0x1e6f20a0); 97 } 98 } 99