1 /* 2 * (C) Copyright ASPEED Technology Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <debug_uart.h> 8 #include <spl.h> 9 #include <dm.h> 10 #include <mmc.h> 11 #include <xyzModem.h> 12 #include <asm/io.h> 13 #include <asm/arch/aspeed_verify.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #define AST_BOOTMODE_SPI 0 18 #define AST_BOOTMODE_EMMC 1 19 #define AST_BOOTMODE_UART 2 20 21 #define SCU_BASE 0x1e6e2000 22 #define SCU_SMP_SEC_ENTRY (SCU_BASE + 0x1bc) 23 #define SCU_WPROT2 (SCU_BASE + 0xf04) 24 25 u32 aspeed_bootmode(void); 26 void aspeed_mmc_init(void); 27 static void spl_boot_from_uart_wdt_disable(void); 28 29 void board_init_f(ulong dummy) 30 { 31 #ifndef CONFIG_SPL_TINY 32 struct udevice *dev; 33 spl_early_init(); 34 timer_init(); 35 uclass_get_device(UCLASS_PINCTRL, 0, &dev); 36 preloader_console_init(); 37 dram_init(); 38 aspeed_mmc_init(); 39 spl_boot_from_uart_wdt_disable(); 40 #endif 41 } 42 43 #ifdef CONFIG_SPL_BOARD_INIT 44 void spl_board_init(void) 45 { 46 struct udevice *dev; 47 48 if ((IS_ENABLED(CONFIG_ASPEED_HACE_V1) || IS_ENABLED(CONFIG_ASPEED_HACE)) && 49 uclass_get_device_by_driver(UCLASS_MISC, 50 DM_GET_DRIVER(aspeed_hace), 51 &dev)) { 52 debug("Warning: HACE initialization failure\n"); 53 } 54 } 55 #endif 56 57 u32 spl_boot_device(void) 58 { 59 switch (aspeed_bootmode()) { 60 case AST_BOOTMODE_EMMC: 61 return BOOT_DEVICE_MMC1; 62 case AST_BOOTMODE_SPI: 63 return BOOT_DEVICE_RAM; 64 case AST_BOOTMODE_UART: 65 return BOOT_DEVICE_UART; 66 default: 67 break; 68 } 69 70 return BOOT_DEVICE_NONE; 71 } 72 73 void board_boot_order(u32 *spl_boot_list) 74 { 75 spl_boot_list[0] = spl_boot_device(); 76 spl_boot_list[1] = ASPEED_BOOT_DEVICE_UART; 77 } 78 79 #ifdef CONFIG_SPL_OS_BOOT 80 int spl_start_uboot(void) 81 { 82 /* boot linux */ 83 return 0; 84 } 85 #endif 86 87 void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size) 88 { 89 ulong s_ep; 90 uint8_t os; 91 92 fit_image_get_os(fit, node, &os); 93 94 /* skip if no TEE */ 95 if (os != IH_OS_TEE) 96 return; 97 98 fit_image_get_entry(fit, node, &s_ep); 99 100 /* set & lock secure entrypoint for secondary cores */ 101 writel(s_ep, SCU_SMP_SEC_ENTRY); 102 writel(BIT(17) | BIT(18) | BIT(19), SCU_WPROT2); 103 } 104 105 int board_fit_config_name_match(const char *name) 106 { 107 /* we always use the default configuration */ 108 debug("%s: %s\n", __func__, name); 109 return 0; 110 } 111 112 struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) 113 { 114 return (struct image_header *)(CONFIG_SYS_LOAD_ADDR); 115 } 116 117 static void spl_boot_from_uart_wdt_disable(void) 118 { 119 int boot_mode = aspeed_bootmode(); 120 121 /* Disable ABR WDT for SPI flash and eMMC ABR. */ 122 if (boot_mode == AST_BOOTMODE_UART) { 123 writel(0, 0x1e620064); 124 writel(0, 0x1e6f20a0); 125 } 126 } 127