1/*
2 *  This program is distributed in the hope that it will be useful,
3 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
4 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5 *  GNU General Public License for more details.
6 *
7 *  You should have received a copy of the GNU General Public License
8 *  along with this program; if not, write to the Free Software
9 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
10 */
11/*
12 * Board specific setup info
13 *
14 ******************************************************************************
15 * ASPEED Technology Inc.
16 * AST26x0 DDR3/DDR4 SDRAM controller initialization sequence for FPGA
17 *
18 * Version     : 2
19 * Release date: 2019.02.19
20 *
21 * Priority of fix item:
22 * [P1] = critical
23 * [P2] = nice to have
24 * [P3] = minor
25 *
26 * Change List :
27 * V0 |2018.03.28 : 1.[P1] Initial release for simulation
28 *
29 * Optional define variable
30 * 1. ECC Function enable
31 *    ASTMMC_DRAM_ECC             // define to enable ECC function
32 *    ASTMMC_DRAM_ECC_SIZE        // define the ECC protected memory size
33 * 2. UART5 message output        //
34 *    ASTMMC_UART_BASE            // select UART port base
35 * 3. DRAM Type
36 *    ASTMMC_DDR4_8GX8            // DDR4 (16Gb) 8Gbit X8 stacked part
37 ******************************************************************************
38 */
39
40#include <config.h>
41#include <version.h>
42#include <asm/secure.h>
43#include <asm/armv7.h>
44
45#ifdef CONFIG_CPU_ARM1176
46#define ASTMMC_DDR_DDR3
47#else
48#define ASTMMC_READ_TRAINING
49#endif
50
51/******************************************************************************
52 Calibration Macro Start
53 Usable registers:
54  r0, r1, r2, r3, r5, r6, r7, r8, r9, r10, r11
55 ******************************************************************************/
56#define ASTMMC_INIT_VER      0x02                // 8bit verison number
57#define ASTMMC_INIT_DATE     0x20190219          // Release date
58
59/* PATTERN_TABLE,
60   init_delay_timer,
61   check_delay_timer,
62   clear_delay_timer,
63   print_hex_char,
64   print_hex_byte,
65   print_hex_word,
66   print_hex_dword,
67   are for DRAM calibration */
68
69#define ASTMMC_UART_BASE     0x1E784000
70
71#ifdef CONFIG_DRAM_ECC
72#define ASTMMC_DRAM_ECC
73#define ASTMMC_DRAM_ECC_SIZE CONFIG_DRAM_ECC_SIZE
74#else
75#define ASTMMC_DRAM_ECC_SIZE 0x0
76#endif
77
78#define ASTMMC_REG_MCR10     0x00
79#define ASTMMC_REG_MCR14     0x04
80#define ASTMMC_REG_MCR18     0x08
81#define ASTMMC_REG_MCR1C     0x0C
82#define ASTMMC_REG_MCR20     0x10
83#define ASTMMC_REG_MCR24     0x14
84#define ASTMMC_REG_MCR28     0x18
85#define ASTMMC_REG_MCR2C     0x1C
86#define ASTMMC_REG_RFC       0x20
87
88TIME_TABLE_DDR3:
89    .word   0x02070306       // MCR10
90    .word   0x05021133       // MCR14
91    .word   0x06010200       // MCR18
92    .word   0x00000020       // MCR1C
93    .word   0x00071320       // MCR20
94    .word   0x00000200       // MCR24
95    .word   0x00000000       // MCR28
96    .word   0x00000000       // MCR2C
97    .word   0x17263434       // MCRFC
98TIME_TABLE_DDR4:
99    .word   0x030C0207       // MCR10
100    .word   0x04451133       // MCR14
101    .word   0x0E010200       // MCR18
102    .word   0x00000140       // MCR1C
103    .word   0x03010100       // MCR20
104    .word   0x00000000       // MCR24
105    .word   0x04C00000       // MCR28
106    .word   0x00000050       // MCR2C
107    .word   0x17263434       // MCRFC
108
109PATTERN_TABLE:
110    .word   0xff00ff00
111    .word   0xcc33cc33
112    .word   0xaa55aa55
113    .word   0x88778877
114    .word   0x92cc4d6e       // 5
115    .word   0x543d3cde
116    .word   0xf1e843c7
117    .word   0x7c61d253
118    .word   0x00000000       // 8
119
120    .macro init_delay_timer
121    ldr   r0, =0x1e782024                        // Set Timer3 Reload
122    str   r2, [r0]
123
124    ldr   r0, =0x1e782034                        // Clear Timer3 ISR
125    ldr   r1, =0x00000004
126    str   r1, [r0]
127
128    ldr   r0, =0x1e782030                        // Enable Timer3
129    mov   r2, #7
130    mov   r1, r2, lsl #8
131    str   r1, [r0]
132
133    ldr   r0, =0x1e782034                        // Check ISR for Timer3 timeout
134    .endm
135
136    .macro check_delay_timer
137    ldr   r1, [r0]
138    bic   r1, r1, #0xFFFFFFFB
139    mov   r2, r1, lsr #2
140    cmp   r2, #0x01
141    .endm
142
143    .macro clear_delay_timer
144    ldr   r0, =0x1e78203C                        // Disable Timer3
145    mov   r2, #0xF
146    mov   r1, r2, lsl #8
147    str   r1, [r0]
148
149    ldr   r0, =0x1e782034                        // Clear Timer3 ISR
150    ldr   r1, =0x00000004
151    str   r1, [r0]
152    .endm
153
154    .macro print_hex_char
155    and   r1, r1, #0xF
156    cmp   r1, #9
157    addgt r1, r1, #0x37
158    addle r1, r1, #0x30
159    str   r1, [r0]
160    .endm
161
162    .macro print_hex_byte
163    ldr   r0, =ASTMMC_UART_BASE
164    mov   r1, r2, lsr #4
165    print_hex_char
166    mov   r1, r2
167    print_hex_char
168    .endm
169
170    .macro print_hex_word
171    ldr   r0, =ASTMMC_UART_BASE
172    mov   r1, r2, lsr #12
173    print_hex_char
174    mov   r1, r2, lsr #8
175    print_hex_char
176    mov   r1, r2, lsr #4
177    print_hex_char
178    mov   r1, r2
179    print_hex_char
180    .endm
181
182    .macro print_hex_dword
183    ldr   r0, =ASTMMC_UART_BASE
184    mov   r1, r2, lsr #28
185    print_hex_char
186    mov   r1, r2, lsr #24
187    print_hex_char
188    mov   r1, r2, lsr #20
189    print_hex_char
190    mov   r1, r2, lsr #16
191    print_hex_char
192    mov   r1, r2, lsr #12
193    print_hex_char
194    mov   r1, r2, lsr #8
195    print_hex_char
196    mov   r1, r2, lsr #4
197    print_hex_char
198    mov   r1, r2
199    print_hex_char
200    .endm
201
202/******************************************************************************
203 Calibration Macro End
204 ******************************************************************************/
205
206.globl lowlevel_init
207lowlevel_init:
208
209#ifndef CONFIG_CPU_ARM1176
210  /* Put secondary core to sleep */
211  mrc   p15, 0, r0, c0, c0, 5                  @; Read CPU ID register
212  ands  r0, r0, #0x03                          @; Mask off, leaving the CPU ID field
213#ifdef CONFIG_ASPEED_NONSECUR_MODE
214  blne	secondary_cpu_init
215#else
216  blne  relocate
217  @blne  wait_for_kickup
218  b     init_uart
219#endif
220
221#if 1
222relocate:
223    adrl  r0, wait_for_kickup
224    ldr   r1, =0x1000f000     //  ; r1 = pointer to destination block
225    mov   r2, #0x20           //  ; r2 = number of words to copy
226wordcopy:
227    ldr   r3, [r0], #4         // ; load a word from the source and
228    str   r3, [r1], #4         // ; store it to the destination
229    subs  r2, r2, #1           // ; decrement the counter
230    bne   wordcopy             //1 ; ... copy more
231
232   	ldr r0, =0x1E6E2180
233	LDR r1, =0x1e784000
234	ldr r4, =0xABBAADDA
235	ldr r3, =0x1E6E2184
236
237   	ldr   r5, =0x10000000
238   	ldr   r6, =0x1000f000
239   	str   r6, [r5]
240	mov   lr, r6
241	mov   pc, lr
242#endif
243#endif
244
245init_uart:
246
247#ifdef CONFIG_SPL_BUILD
248    /* leave the rest to U-Boot proper */
249    mov   r1, #0
250    ldr   r0, =0x1e78500c
251    str   r1, [r0]
252    ldr   r0, =0x1e78504c
253    str   r1, [r0]
254    ldr   r0, =0x1e78508c
255    str   r1, [r0]
256    ldr   r0, =0x1e7850cc
257    str   r1, [r0]
258
259    mov   pc, lr
260#endif
261
262    /* save lr */
263    mov   r4, lr
264
265    /*Initialize the Debug UART here*/
266    ldr   r0, =(ASTMMC_UART_BASE | 0x0c)
267    mov   r1, #0x83
268    str   r1, [r0]
269
270    ldr   r0, =(ASTMMC_UART_BASE | 0x00)
271    mov   r1, #0x01
272    str   r1, [r0]
273
274    ldr   r0, =(ASTMMC_UART_BASE | 0x04)
275    mov   r1, #0x00
276    str   r1, [r0]
277
278    ldr   r0, =(ASTMMC_UART_BASE | 0x0c)
279    mov   r1, #0x03
280    str   r1, [r0]
281
282    ldr   r0, =(ASTMMC_UART_BASE | 0x08)
283    mov   r1, #0x07
284    str   r1, [r0]
285
286init_dram:
287
288/* Test - DRAM initial time */
289    ldr   r0, =0x1e78203c
290    ldr   r1, =0x0000F000
291    str   r1, [r0]
292
293    ldr   r0, =0x1e782044
294    ldr   r1, =0xFFFFFFFF
295    str   r1, [r0]
296
297    ldr   r0, =0x1e782030
298    ldr   r1, =0x00003000
299    str   r1, [r0]
300/* Test - DRAM initial time */
301
302    /*Set Scratch register Bit 7 before initialize*/
303    ldr   r0, =0x1e6e2000
304    ldr   r1, =0x1688a8a8
305    str   r1, [r0]
306    ldr   r0, =0x1e6e2010
307    str   r1, [r0]
308
309/*  ldr   r0, =0x1e6e2100
310    ldr   r1, [r0]
311    orr   r1, r1, #0x80
312    str   r1, [r0]
313*/
314/******************************************************************************
315 Disable WDT for SPI Address mode detection function
316 ******************************************************************************/
317    ldr   r0, =0x1e620060
318    mov   r1, #0
319    str   r1, [r0]
320
321    ldr   r0, =0x1e620064
322    mov   r1, #0
323    str   r1, [r0]
324
325    ldr   r0, =0x1e78500c
326    mov   r1, #0
327    str   r1, [r0]
328    ldr   r0, =0x1e78504c
329    str   r1, [r0]
330    ldr   r0, =0x1e78508c
331    str   r1, [r0]
332    ldr   r0, =0x1e7850cc
333    str   r1, [r0]
334
335#ifdef CONFIG_CPU_ARM1176
336    /* Enable AXI_P */
337/*  ldr   r0, =0x00000016
338    mrc   p15, 0, r1, c15, c2, 4
339    mcr   p15, 0, r0, c15, c2, 4
340*/
341init_arm11:
342    /* Start of ES40004A PLL init */
343    /* Step 1. Program PLL_config and keep power down */
344    ldr   r0, =0x33000000
345    ldr   r1, =0x01000000
346    str   r1, [r0]
347    ldr   r1, =0x0102001A                        @ 324 MHz
348    str   r1, [r0]
349
350    /* Step 2. Wait 1us for PLL initialization */
351    ldr   r2, =0x00000100
352delay_ES40004A_pll_init:
353    subs  r2, r2, #1
354    bne   delay_ES40004A_pll_init
355
356    /* Step 3. Program PLL_config to exit Power down */
357    ldr   r1, =0x0002001A
358    str   r1, [r0]
359
360    /* Step 4. Check pll_ld = 1?. Read PLL_config, check bit 27. */
361    ldr   r2, =0x08000000                        @ bit[27] PLL lock detection
362check_pll_ld:
363    ldr   r1, [r0]
364    tst   r1, r2
365    beq   check_pll_ld
366
367    /* Step 5. Program aclk_div */
368    ldr   r0, =0x33000004
369    ldr   r1, =0x00000007                        @ CPU/AXI = 8/1
370    str   r1, [r0]
371
372    /* Step 6. Program set_pll */
373    ldr   r1, =0x00010007
374    str   r1, [r0]
375    /* End of ES40004A PLL init */
376#endif
377
378    /* skip SDRAM initialization (will be done in C function) */
379    b     platform_exit
380
381platform_exit:
382    /* restore lr */
383    mov   lr, r4
384
385    /* back to arch calling code */
386    mov   pc, lr
387
388secondary_cpu_init:
389#ifdef CONFIG_ASPEED_NONSECUR_MODE
390    mov   r6,pc
391	bl    start_sec
392#endif
393wait_for_kickup:
394	wfe
395	ldr r2,[r3]
396	cmp r2,r4
397	bne wait_for_kickup
398
399	MOV r2,#'['
400	STR r2,[r1]
401	MOV r2,#'1'
402	STR r2,[r1]
403	MOV r2,#'C'
404	STR r2,[r1]
405	MOV r2,#'P'
406	STR r2,[r1]
407	MOV r2,#'U'
408	STR r2,[r1]
409	MOV r2,#']'
410	STR r2,[r1]
411	MOV r2,#'\n'
412	STR r2,[r1]
413	MOV r2,#'\r'
414	STR r2,[r1]
415	ldr pc, [r0]
416	ldr pc, [r0]
417	b wait_for_kickup
418