1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) ASPEED Technology Inc. 4 * Chia-Wei Wang <chiawei_wang@aspeedtech.com> 5 */ 6 7#include <config.h> 8#include <version.h> 9#include <asm/secure.h> 10#include <asm/armv7.h> 11#include <linux/linkage.h> 12 13/* 14 * SMP mailbox 15 * +----------------------+ 16 * | | 17 * | mailbox insn. for | 18 * | cpuN polling SMP go | 19 * | | 20 * +----------------------+ 0xC 21 * | mailbox ready signal | 22 * +----------------------+ 0x8 23 * | cpuN GO signal | 24 * +----------------------+ 0x4 25 * | cpuN entrypoint | 26 * +----------------------+ AST_SMP_MAILBOX_BASE 27 */ 28 29#define AST_SMP_MAILBOX_BASE 0x1E6E2180 30#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 31#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 32#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 33#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 34 35/* AST2600 HW registers */ 36#define AST_SCU_BASE 0x1E6E2000 37#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) 38#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) 39#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) 40#define AST_SCU_SYSRST_CTRL (AST_SCU_BASE + 0x040) 41#define AST_SCU_SYSRST_CTRL_CLR (AST_SCU_BASE + 0x044) 42#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) 43#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) 44#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) 45#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) 46#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) 47 48#define AST_FMC_BASE 0x1E620000 49#define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) 50#define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) 51 52/* Revision ID */ 53#define REV_ID_AST2600A0 0x05000303 54 55ENTRY(ast_bootmode) 56 ldr r1, =AST_SCU_HW_STRAP1 57 ldr r0, [r1] 58 tst r0, #0x4 59 moveq r0, #0x0 @; AST_BOOTMODE_SPI 60 movne r0, #0x1 @; AST_BOOTMODE_EMMC 61 mov pc, lr 62ENDPROC(ast_bootmode) 63 64.macro scu_unlock 65 movw r0, #0xA8A8 66 movt r0, #0x1688 @; magic key to unlock SCU 67 68 ldr r1, =AST_SCU_PROT_KEY1 69 str r0, [r1] 70 ldr r1, =AST_SCU_PROT_KEY2 71 str r0, [r1] 72.endm 73 74.macro timer_init 75#ifdef CONFIG_FPGA_ASPEED 76 movw r0, #0xF080 77 movt r0, #0x2FA 78#else 79 movw r0, #0x2340 80 movt r0, #0x430E 81#endif 82 mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ 83.endm 84 85 86.globl lowlevel_init 87 88lowlevel_init: 89#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 90 mov pc, lr 91#else 92 /* setup ARM arch timer frequency */ 93 timer_init 94 95 /* reset SMP mailbox as early as possible */ 96 mov r0, #0x0 97 ldr r1, =AST_SMP_MBOX_FIELD_READY 98 str r0, [r1] 99 100 /* set ACTLR.SMP to enable cache use */ 101 mrc p15, 0, r0, c1, c0, 1 102 orr r0, #0x40 103 mcr p15, 0, r0, c1, c0, 1 104 105 /* 106 * we treat cpu0 as the primary core and 107 * put secondary core (cpuN) to sleep 108 */ 109 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 110 ands r0, #0xFF @; Mask off, leaving the CPU ID field 111 movw r2, #0xAB00 112 movt r2, #0xABBA 113 orr r2, r0 114 115 beq do_primary_core_setup 116 117 /* hold cpuN until mailbox is ready */ 118poll_mailbox_ready: 119 wfe 120 ldr r0, =AST_SMP_MBOX_FIELD_READY 121 ldr r0, [r0] 122 movw r1, #0xCAFE 123 movt r1, #0xBABE 124 cmp r1, r0 125 bne poll_mailbox_ready 126 127 /* parameters for relocated SMP go polling insn. */ 128 ldr r0, =AST_SMP_MBOX_FIELD_GOSIGN 129 ldr r1, =AST_SMP_MBOX_FIELD_ENTRY 130 131 /* no return */ 132 ldr pc, =AST_SMP_MBOX_FIELD_POLLINSN 133 134do_primary_core_setup: 135 /* unlock system control unit */ 136 scu_unlock 137 138 /* tune-up CPU clock for AST2600 A0 */ 139 ldr r0, =AST_SCU_REV_ID 140 ldr r0, [r0] 141 142 ldr r1, =REV_ID_AST2600A0 143 cmp r0, r1 144 145 bne 0f 146 147 /* setup CPU clocks */ 148 ldr r0, =AST_SCU_HW_STRAP1 149 ldr r1, [r0] 150 bic r1, #0x1800 151 orr r1, #0x1000 152 str r1, [r0] 153 154 ldr r0, =AST_SCU_HPLL_PARAM 155 movw r1, #0x4087 156 movt r1, #0x1000 157 str r1, [r0] 158 159 ldr r0, =AST_SCU_HPLL_PARAM_EXT 160 mov r1, #0x47 161 str r1, [r0] 162 163wait_lock: 164 ldr r1, [r0] 165 tst r1, #0x80000000 166 beq wait_lock 167 1680: 169 /* enable cache & SRAM parity check */ 170 mov r0, #0 171 ldr r1, =AST_SCU_CA7_PARITY_CLR 172 str r0, [r1] 173 174 mov r0, #0x11 175 ldr r1, =AST_SCU_CA7_PARITY_CHK 176 str r0, [r1] 177 178 /* disable FMC WDT for SPI address mode detection */ 179 mov r0, #0 180 ldr r1, =AST_FMC_WDT1_CTRL_MODE 181 str r0, [r1] 182#if 0 183 ldr r1, =AST_FMC_WDT2_CTRL_MODE 184 str r0, [r1] 185#endif 186 187 /* release display port reset */ 188 ldr r0, =AST_SCU_SYSRST_CTRL_CLR 189 movw r1, #0x0000 190 movt r1, #0x3000 191 str r1, [r0] 192 193 /* relocate mailbox insn. for cpuN polling SMP go signal */ 194 adrl r0, mailbox_insn 195 adrl r1, mailbox_insn_end 196 197 ldr r2, =#AST_SMP_MBOX_FIELD_POLLINSN 198 199relocate_mailbox_insn: 200 ldr r3, [r0], #0x4 201 str r3, [r2], #0x4 202 cmp r0, r1 203 bne relocate_mailbox_insn 204 205 /* reset SMP go sign */ 206 mov r0, #0 207 ldr r1, =AST_SMP_MBOX_FIELD_GOSIGN 208 str r0, [r1] 209 210 /* notify cpuN mailbox is ready */ 211 movw r0, #0xCAFE 212 movt r0, #0xBABE 213 ldr r1, =AST_SMP_MBOX_FIELD_READY 214 str r0, [r1] 215 sev 216 217 /* back to arch calling code */ 218 mov pc, lr 219 220/* 221 * insn. inside mailbox to poll SMP go signal. 222 * 223 * Note that as this code will be relocated, any 224 * pc-relative assembly should NOT be used. 225 */ 226mailbox_insn: 227 /* 228 * r0 ~ r3 are parameters: 229 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 230 * r1 = AST_SMP_MBOX_FIELD_ENTRY 231 * r2 = per-cpu go sign value 232 * r3 = no used now 233 */ 234poll_mailbox_smp_go: 235 wfe 236 ldr r4, [r0] 237 cmp r2, r4 238 bne poll_mailbox_smp_go 239 240 /* SMP GO signal confirmed, release cpuN */ 241 ldr pc, [r1] 242 243mailbox_insn_end: 244 /* should never reach */ 245 b . 246 247#endif 248