1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2016 Google, Inc
4  */
5 #include <common.h>
6 #include <dm.h>
7 #include <ram.h>
8 #include <timer.h>
9 #include <asm/io.h>
10 #include <asm/arch/timer.h>
11 #include <linux/bitops.h>
12 #include <linux/err.h>
13 #include <dm/uclass.h>
14 
15 DECLARE_GLOBAL_DATA_PTR;
16 
17 /*
18  * RMII daughtercard workaround
19  */
20 //#define ASPEED_RMII_DAUGHTER_CARD
21 
22 #ifdef ASPEED_RMII_DAUGHTER_CARD
23 /**
24  * @brief	workaround for RMII daughtercard, reset PHY manually
25  *
26  * workaround for Aspeed RMII daughtercard, reset Eth PHY by GPO F0 and F2
27  * Where GPO F0 controls the reset signal of RMII PHY 1 and 2.
28  * Where GPO F2 controls the reset signal of RMII PHY 3 and 4.
29 */
30 void reset_eth_phy(void)
31 {
32 #define GRP_F		8
33 #define PHY_RESET_MASK  (BIT(GRP_F + 0) | BIT(GRP_F + 2))
34 
35 	u32 value = readl(0x1e780020);
36 	u32 direction = readl(0x1e780024);
37 
38 	debug("RMII workaround: reset PHY manually\n");
39 
40 	direction |= PHY_RESET_MASK;
41 	value &= ~PHY_RESET_MASK;
42 	writel(direction, 0x1e780024);
43 	writel(value, 0x1e780020);
44 	while((readl(0x1e780020) & PHY_RESET_MASK) != 0);
45 
46 	udelay(1000);
47 
48 	value |= PHY_RESET_MASK;
49 	writel(value, 0x1e780020);
50 	while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK);
51 }
52 #endif
53 
54 __weak int board_init(void)
55 {
56 	struct udevice *dev;
57 	int i;
58 	int ret;
59 
60 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
61 
62 #ifdef ASPEED_RMII_DAUGHTER_CARD
63 	reset_eth_phy();
64 #endif
65 	/*
66 	 * Loop over all MISC uclass drivers to call the comphy code
67 	 * and init all CP110 devices enabled in the DT
68 	 */
69 	i = 0;
70 	while (1) {
71 		/* Call the comphy code via the MISC uclass driver */
72 		ret = uclass_get_device(UCLASS_MISC, i++, &dev);
73 
74 		/* We're done, once no further CP110 device is found */
75 		if (ret)
76 			break;
77 	}
78 
79 	return 0;
80 }
81 
82 __weak int dram_init(void)
83 {
84 	struct udevice *dev;
85 	struct ram_info ram;
86 	int ret;
87 
88 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
89 	if (ret) {
90 		debug("DRAM FAIL1\r\n");
91 		return ret;
92 	}
93 
94 	ret = ram_get_info(dev, &ram);
95 	if (ret) {
96 		debug("DRAM FAIL2\r\n");
97 		return ret;
98 	}
99 
100 	gd->ram_size = ram.size;
101 	return 0;
102 }
103 
104 int arch_early_init_r(void)
105 {
106 #ifdef CONFIG_DM_PCI
107 	/* Trigger PCIe devices detection */
108 	pci_init();
109 #endif
110 
111 	return 0;
112 }
113 
114 void board_add_ram_info(int use_default)
115 {
116 #define MMC_BASE 0x1e6e0000
117 #define SCU_BASE 0x1e6e2000
118 	uint32_t act_size = 256 << (readl(MMC_BASE + 0x04) & 0x3);
119 	uint32_t vga_rsvd = 8 << ((readl(MMC_BASE + 0x04) >> 2) & 0x3);
120 	uint8_t ecc = (readl(MMC_BASE + 0x04) >> 7) & 0x1;
121 
122 	/* no VGA reservation if efuse VGA disable bit is set */
123 	if (readl(SCU_BASE + 0x594) & BIT(14))
124 		vga_rsvd = 0;
125 
126 	printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size,
127 	       vga_rsvd, ecc == 1 ? "on" : "off");
128 }
129 
130 union ast2600_pll_reg {
131 	unsigned int w;
132 	struct {
133 		unsigned int m : 13;		/* bit[12:0]	*/
134 		unsigned int n : 6;		/* bit[18:13]	*/
135 		unsigned int p : 4;		/* bit[22:19]	*/
136 		unsigned int off : 1;		/* bit[23]	*/
137 		unsigned int bypass : 1;	/* bit[24]	*/
138 		unsigned int reset : 1;		/* bit[25]	*/
139 		unsigned int reserved : 6;	/* bit[31:26]	*/
140 	} b;
141 };
142 
143 void aspeed_mmc_init(void)
144 {
145 	u32 reset_bit;
146 	u32 clkstop_bit;
147 	u32 clkin = 25000000;
148 	u32 pll_reg = 0;
149 	u32 enableclk_bit;
150 	u32 rate = 0;
151 	u32 div = 0;
152 	u32 i = 0;
153 	u32 mult;
154 	u32 clk_sel = readl(0x1e6e2300);
155 
156 	/* check whether boot from eMMC is enabled */
157 	if ((readl(0x1e6e2500) & 0x4) == 0)
158 		return;
159 
160 	/* disable eMMC boot controller engine */
161 	*(volatile int *)0x1e6f500C &= ~0x90000000;
162 	/* set pinctrl for eMMC */
163 	*(volatile int *)0x1e6e2400 |= 0xff000000;
164 
165 	/* clock setting for eMMC */
166 	enableclk_bit = BIT(15);
167 
168 	reset_bit = BIT(16);
169 	clkstop_bit = BIT(27);
170 	writel(reset_bit, 0x1e6e2040);
171 	udelay(100);
172 	writel(clkstop_bit, 0x1e6e2084);
173 	mdelay(10);
174 	writel(reset_bit, 0x1e6e2044);
175 
176 	pll_reg = readl(0x1e6e2220);
177 	if (pll_reg & BIT(24)) {
178 		/* Pass through mode */
179 		mult = div = 1;
180 	} else {
181 		/* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
182 		union ast2600_pll_reg reg;
183 		reg.w = pll_reg;
184 		mult = (reg.b.m + 1) / (reg.b.n + 1);
185 		div = (reg.b.p + 1);
186 	}
187 	rate = ((clkin * mult)/div);
188 
189 	for(i = 0; i < 8; i++) {
190 		div = (i + 1) * 2;
191 		if ((rate / div) <= 200000000)
192 			break;
193 	}
194 
195 	clk_sel &= ~(0x7 << 12);
196 	clk_sel |= (i << 12) | BIT(11);
197 	writel(clk_sel, 0x1e6e2300);
198 
199 	setbits_le32(0x1e6e2300, enableclk_bit);
200 
201 	return;
202 
203 }
204 
205