1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #include <common.h> 6 #include <dm.h> 7 #include <ram.h> 8 #include <timer.h> 9 #include <asm/io.h> 10 #include <asm/arch/timer.h> 11 #include <linux/err.h> 12 #include <dm/uclass.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 /* 17 * RMII daughtercard workaround 18 */ 19 //#define ASPEED_RMII_DAUGHTER_CARD 20 21 #ifdef ASPEED_RMII_DAUGHTER_CARD 22 /** 23 * @brief workaround for RMII daughtercard, reset PHY manually 24 * 25 * workaround for Aspeed RMII daughtercard, reset Eth PHY by GPO F0 and F2 26 * Where GPO F0 controls the reset signal of RMII PHY 1 and 2. 27 * Where GPO F2 controls the reset signal of RMII PHY 3 and 4. 28 */ 29 void reset_eth_phy(void) 30 { 31 #define GRP_F 8 32 #define PHY_RESET_MASK (BIT(GRP_F + 0) | BIT(GRP_F + 2)) 33 34 u32 value = readl(0x1e780020); 35 u32 direction = readl(0x1e780024); 36 37 debug("RMII workaround: reset PHY manually\n"); 38 39 direction |= PHY_RESET_MASK; 40 value &= ~PHY_RESET_MASK; 41 writel(direction, 0x1e780024); 42 writel(value, 0x1e780020); 43 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); 44 45 udelay(1000); 46 47 value |= PHY_RESET_MASK; 48 writel(value, 0x1e780020); 49 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); 50 } 51 #endif 52 53 __weak int board_init(void) 54 { 55 struct udevice *dev; 56 int i; 57 int ret; 58 59 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 60 61 #ifdef ASPEED_RMII_DAUGHTER_CARD 62 reset_eth_phy(); 63 #endif 64 /* 65 * Loop over all MISC uclass drivers to call the comphy code 66 * and init all CP110 devices enabled in the DT 67 */ 68 i = 0; 69 while (1) { 70 /* Call the comphy code via the MISC uclass driver */ 71 ret = uclass_get_device(UCLASS_MISC, i++, &dev); 72 73 /* We're done, once no further CP110 device is found */ 74 if (ret) 75 break; 76 } 77 78 return 0; 79 } 80 81 __weak int dram_init(void) 82 { 83 struct udevice *dev; 84 struct ram_info ram; 85 int ret; 86 87 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 88 if (ret) { 89 debug("DRAM FAIL1\r\n"); 90 return ret; 91 } 92 93 ret = ram_get_info(dev, &ram); 94 if (ret) { 95 debug("DRAM FAIL2\r\n"); 96 return ret; 97 } 98 99 gd->ram_size = ram.size; 100 return 0; 101 } 102 103 int arch_early_init_r(void) 104 { 105 #ifdef CONFIG_DM_PCI 106 /* Trigger PCIe devices detection */ 107 pci_init(); 108 #endif 109 110 return 0; 111 } 112 113