1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 #include <common.h> 6 #include <dm.h> 7 #include <ram.h> 8 #include <timer.h> 9 #include <asm/io.h> 10 #include <asm/arch/timer.h> 11 #include <linux/bitops.h> 12 #include <linux/err.h> 13 #include <dm/uclass.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 /* 18 * RMII daughtercard workaround 19 */ 20 //#define ASPEED_RMII_DAUGHTER_CARD 21 22 #ifdef ASPEED_RMII_DAUGHTER_CARD 23 /** 24 * @brief workaround for RMII daughtercard, reset PHY manually 25 * 26 * workaround for Aspeed RMII daughtercard, reset Eth PHY by GPO F0 and F2 27 * Where GPO F0 controls the reset signal of RMII PHY 1 and 2. 28 * Where GPO F2 controls the reset signal of RMII PHY 3 and 4. 29 */ 30 void reset_eth_phy(void) 31 { 32 #define GRP_F 8 33 #define PHY_RESET_MASK (BIT(GRP_F + 0) | BIT(GRP_F + 2)) 34 35 u32 value = readl(0x1e780020); 36 u32 direction = readl(0x1e780024); 37 38 debug("RMII workaround: reset PHY manually\n"); 39 40 direction |= PHY_RESET_MASK; 41 value &= ~PHY_RESET_MASK; 42 writel(direction, 0x1e780024); 43 writel(value, 0x1e780020); 44 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); 45 46 udelay(1000); 47 48 value |= PHY_RESET_MASK; 49 writel(value, 0x1e780020); 50 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); 51 } 52 #endif 53 54 __weak int board_init(void) 55 { 56 struct udevice *dev; 57 int i; 58 int ret; 59 u64 rev_id; 60 u32 tmp_val; 61 62 /* disable address remapping for A1 to prevent secure boot reboot failure */ 63 rev_id = readl(ASPEED_REVISION_ID0); 64 rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id; 65 66 if (rev_id == 0x0501030305010303 || rev_id == 0x0501020305010203) { 67 if ((readl(ASPEED_SB_STS) & BIT(6))) { 68 tmp_val = readl(0x1e60008c) & (~BIT(0)); 69 writel(0xaeed1a03, 0x1e600000); 70 writel(tmp_val, 0x1e60008c); 71 writel(0x1, 0x1e600000); 72 } 73 } 74 75 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 76 77 #ifdef ASPEED_RMII_DAUGHTER_CARD 78 reset_eth_phy(); 79 #endif 80 /* 81 * Loop over all MISC uclass drivers to call the comphy code 82 * and init all CP110 devices enabled in the DT 83 */ 84 i = 0; 85 while (1) { 86 /* Call the comphy code via the MISC uclass driver */ 87 ret = uclass_get_device(UCLASS_MISC, i++, &dev); 88 89 /* We're done, once no further CP110 device is found */ 90 if (ret) 91 break; 92 } 93 94 return 0; 95 } 96 97 __weak int dram_init(void) 98 { 99 struct udevice *dev; 100 struct ram_info ram; 101 int ret; 102 103 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 104 if (ret) { 105 debug("DRAM FAIL1\r\n"); 106 return ret; 107 } 108 109 ret = ram_get_info(dev, &ram); 110 if (ret) { 111 debug("DRAM FAIL2\r\n"); 112 return ret; 113 } 114 115 gd->ram_size = ram.size; 116 return 0; 117 } 118 119 int arch_early_init_r(void) 120 { 121 #ifdef CONFIG_DM_PCI 122 /* Trigger PCIe devices detection */ 123 pci_init(); 124 #endif 125 126 return 0; 127 } 128 129 void board_add_ram_info(int use_default) 130 { 131 #define MMC_BASE 0x1e6e0000 132 #define SCU_BASE 0x1e6e2000 133 uint32_t act_size = 256 << (readl(MMC_BASE + 0x04) & 0x3); 134 uint32_t vga_rsvd = 8 << ((readl(MMC_BASE + 0x04) >> 2) & 0x3); 135 uint8_t ecc = (readl(MMC_BASE + 0x04) >> 7) & 0x1; 136 137 /* no VGA reservation if efuse VGA disable bit is set */ 138 if (readl(SCU_BASE + 0x594) & BIT(14)) 139 vga_rsvd = 0; 140 141 printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size, 142 vga_rsvd, ecc == 1 ? "on" : "off"); 143 } 144 145 union ast2600_pll_reg { 146 unsigned int w; 147 struct { 148 unsigned int m : 13; /* bit[12:0] */ 149 unsigned int n : 6; /* bit[18:13] */ 150 unsigned int p : 4; /* bit[22:19] */ 151 unsigned int off : 1; /* bit[23] */ 152 unsigned int bypass : 1; /* bit[24] */ 153 unsigned int reset : 1; /* bit[25] */ 154 unsigned int reserved : 6; /* bit[31:26] */ 155 } b; 156 }; 157 158 void aspeed_mmc_init(void) 159 { 160 u32 reset_bit; 161 u32 clkstop_bit; 162 u32 clkin = 25000000; 163 u32 pll_reg = 0; 164 u32 enableclk_bit; 165 u32 rate = 0; 166 u32 div = 0; 167 u32 i = 0; 168 u32 mult; 169 u32 clk_sel = readl(0x1e6e2300); 170 171 /* check whether boot from eMMC is enabled */ 172 if ((readl(0x1e6e2500) & 0x4) == 0) 173 return; 174 175 /* disable eMMC boot controller engine */ 176 *(volatile int *)0x1e6f500C &= ~0x90000000; 177 /* set pinctrl for eMMC */ 178 *(volatile int *)0x1e6e2400 |= 0xff000000; 179 180 /* clock setting for eMMC */ 181 enableclk_bit = BIT(15); 182 183 reset_bit = BIT(16); 184 clkstop_bit = BIT(27); 185 writel(reset_bit, 0x1e6e2040); 186 udelay(100); 187 writel(clkstop_bit, 0x1e6e2084); 188 mdelay(10); 189 writel(reset_bit, 0x1e6e2044); 190 191 pll_reg = readl(0x1e6e2220); 192 if (pll_reg & BIT(24)) { 193 /* Pass through mode */ 194 mult = div = 1; 195 } else { 196 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ 197 union ast2600_pll_reg reg; 198 reg.w = pll_reg; 199 mult = (reg.b.m + 1) / (reg.b.n + 1); 200 div = (reg.b.p + 1); 201 } 202 rate = ((clkin * mult)/div); 203 204 for(i = 0; i < 8; i++) { 205 div = (i + 1) * 2; 206 if ((rate / div) <= 200000000) 207 break; 208 } 209 210 clk_sel &= ~(0x7 << 12); 211 clk_sel |= (i << 12) | BIT(11); 212 writel(clk_sel, 0x1e6e2300); 213 214 setbits_le32(0x1e6e2300, enableclk_bit); 215 216 return; 217 218 } 219 220