1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST25x0 DDR3/DDR4 SDRAM controller initialization sequence 17 * 18 * Gary Hsu, <gary_hsu@aspeedtech.com> 19 * 20 * Version : 18 21 * Release date: 2017.10.27 22 * 23 * Priority of fix item: 24 * [P1] = critical 25 * [P2] = nice to have 26 * [P3] = minor 27 * 28 * Change List : 29 * V2 |2014.07.25 : 1.[P1] Modify HPLL config sequence 30 * V2 |2014.07.30 : 1.[P1] Modify DDR3 AC parameters table 31 * | 2.[P1] Turn on ZQCS mode 32 * V2 |2014.08.13 : 1.[P1] Add disable XDMA 33 * V2 |2014.09.09 : 1.[P1] Disable CKE dynamic power down 34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1) 35 * V2 |2015.03.26 : 1.[P1] Revise AC timing table 36 * | 2.[P1] Add check code to bypass A0 patch 37 * | 3.[P1] Add MPLL parameter of A1 38 * | 4.[P1] Set X-DMA into VGA memory domain 39 * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init 40 * | 2.[P1] Set MCR1C & MCR38 41 * V3 |2015.05.13 : 1.[P1] Modify DDR4 PHY Vref training algorithm 42 * | 2.[P2] Enable CKE dynamic power down 43 * V4 |2015.06.15 : 1.[P1] Add MAC timing setting 44 * V5 |2015.07.09 : 1.[P1] Modify MHCLK divider ratio 45 * | 2.[P2] Add DDR read margin report 46 * V6 |2015.08.13 : 1.[P3] Disable MMC password before exit 47 * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition 48 * V7 |2015.09.18 : 1.[P1] Clear AHB bus lock condition at power up time 49 * | 2.[P1] Add reset MMC controller to solve init DRAM again during VGA ON 50 * V7 |2015.09.22 : 1.[P1] Add watchdog full reset for resolving reset incomplete issue at fast reset condition 51 * | 2.[P1] Add DRAM stress test after train complete, and redo DRAM initial if stress fail 52 * | 3.[P2] Enable JTAG master mode 53 * | 4.[P2] Add DDR4 Vref trainig retry timeout 54 * V8 |2015.11.02 : 1.[P2] Clear software strap flag before doing watchdog full reset 55 * |2015.12.10 : 1.[P1] Add USB PHY initial code 56 * |2016.01.27 : 1.[P3] Modify the first reset from full chip reset to SOC reset 57 * | 2.[P3] Remove HPLL/MPLL patch code for revision A0 58 * | 3.[P2] Move the reset_mmc code to be after MPLL initialized 59 * V9 |2016.02.19 : 1.[P3] Remove definition "CONFIG_FIRMWARE_2ND_BOOT" 60 * V10|2016.04.21 : 1.[P1] Add USB PHY initial code - port B, to prevent wrong state on USB pins 61 * V11|2016.05.10 : 1.[P3] Add DRAM Extended temperature range support 62 * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled 63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204 64 * | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0 65 * | : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35 to 0.3. Add "Warning" while violated. 66 * V13|2016.08.29 : 1.[P3] Add option to route debug message output port from UART5 to UART1 67 * |2016.09.02 : 2.[P2] Add range control for cache function when ECC enabled 68 * |2016.09.06 : 3.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough 69 * V14|2016.10.25 : 1.[P2] Change Ron manual calibration to default OFF, customer can enable it to do fine-tuning of the Vix issue 70 * |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training 71 * V15|2017.04.06 : 1.[P1] Modify USB portA initial sequence, this is to prevent DMA lock condition of USB Virtual Hub device for some chips. 72 * |2017.04.13 : 2.[P2] Add initial sequence for LPC controller 73 * V16|2017.06.15 : 1.[P1] Add margin check/retry for DDR4 Vref training margin. 74 * |2017.06.15 : 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin. 75 * |2017.06.19 : 3.[P2] Add initial sequence for LPC controller 76 * |2017.06.19 : 4.[P2] Add initial full-chip reset option 77 * |2017.06.19 : 5.[P3] Add 10ms delay after DDR reset 78 * V17|2017.09.25 : 1.[P1] Modify DDR4 side ODT value from 60ohm to 48ohm. 79 * |2017.09.25 : 2.[P1] Add Hynix DDR4 frequency slow down option. 80 * V18|2017.10.26 : 1.[P3] Include the modification of DDR4 side ODT value in V17 into the option of Hynix DDR4 configuration. 81 * |2017.10.26 : 2.[P2] Enhance initial sequence for LPC controller 82 * Note: Read timing report is only a reference, it is not a solid rule for stability. 83 * 84 * Optional define variable 85 * 1. DRAM Speed // 86 * CONFIG_DRAM_1333 // 87 * CONFIG_DRAM_1600 // (default) 88 * 2. ECC Function enable 89 * CONFIG_DRAM_ECC // define to enable ECC function 90 * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size 91 * 3. UART5 message output // 92 * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 93 * CONFIG_DRAM_UART_TO_UART1 // route UART5 to UART port1 94 * 4. DRAM Type 95 * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die 96 * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part 97 * 5. Firmware 2nd boot flash 98 * CONFIG_FIRMWARE_2ND_BOOT (Removed) 99 * 6. Enable DRAM extended temperature range mode 100 * CONFIG_DRAM_EXT_TEMP 101 * 7. Select WDT_Full mode for power up initial reset 102 * ASTMMC_INIT_RESET_MODE_FULL 103 * 8. Hynix DDR4 options 104 * CONFIG_DDR4_SUPPORT_HYNIX // Enable this when Hynix DDR4 included in the BOM 105 * CONFIG_DDR4_HYNIX_SET_1536 106 * CONFIG_DDR4_HYNIX_SET_1488 107 * CONFIG_DDR4_HYNIX_SET_1440 // Default 108 ****************************************************************************** 109 */ 110 111#include <config.h> 112#include <version.h> 113 114/****************************************************************************** 115 r4 : return program counter 116 r5 : DDR speed timing table base address 117 Free registers: 118 r0, r1, r2, r3, r6, r7, r8, r9, r10, r11 119 ******************************************************************************/ 120#define ASTMMC_INIT_VER 0x12 @ 8bit verison number 121#define ASTMMC_INIT_DATE 0x20171027 @ Release date 122 123/****************************************************************************** 124 BMC side DDR IO driving manual mode fine-tuning, used to improve CK/CKN Vix violation. 125 Default disabled, the driver setting is hardware auto tuned. 126 127 ASTMMC_DDR4_MANUAL_RPU | ASTMMC_DDR4_MANUAL_RPD 128 -----------------------+----------------------- 129 No | x : manual mode disabled 130 Yes | No : enable Rpu manual setting 131 Yes | Yes : enable Rpu/Rpd manual setting 132 ******************************************************************************/ 133//#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving 134//#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving 135 136/****************************************************************************** 137 Select initial reset mode as WDT_Full 138 WDT_Full is a more complete reset mode than WDT_SOC. 139 But if FW has other initial code executed before platform.S, then it should use WDT_SOC mode. 140 Use WDT_Full may clear the initial result of prior initial code. 141 ******************************************************************************/ 142//#define ASTMMC_INIT_RESET_MODE_FULL 143 144/****************************************************************************** 145 There is a compatibility issue for Hynix DDR4 SDRAM. 146 Hynix DDR4 SDRAM is more weak on noise margin compared to Micron and Samsung DDR4. 147 To well support Hynix DDR4, it requlres to slow down the DDR4 operating frequency 148 from 1600Mbps to 1536/1488/1440 Mbps. The target frequency that can be used depends 149 on the MB layout. Customer can find the appropriate frequency for their products. 150 Below are the new defined parameters for the Hynix DDR4 supporting. 151 ******************************************************************************/ 152#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM 153//#define CONFIG_DDR4_HYNIX_SET_1536 154//#define CONFIG_DDR4_HYNIX_SET_1488 155#define CONFIG_DDR4_HYNIX_SET_1440 156 157#define ASTMMC_REGIDX_010 0x00 158#define ASTMMC_REGIDX_014 0x04 159#define ASTMMC_REGIDX_018 0x08 160#define ASTMMC_REGIDX_020 0x0C 161#define ASTMMC_REGIDX_024 0x10 162#define ASTMMC_REGIDX_02C 0x14 163#define ASTMMC_REGIDX_030 0x18 164#define ASTMMC_REGIDX_214 0x1C 165#define ASTMMC_REGIDX_2E0 0x20 166#define ASTMMC_REGIDX_2E4 0x24 167#define ASTMMC_REGIDX_2E8 0x28 168#define ASTMMC_REGIDX_2EC 0x2C 169#define ASTMMC_REGIDX_2F0 0x30 170#define ASTMMC_REGIDX_2F4 0x34 171#define ASTMMC_REGIDX_2F8 0x38 172#define ASTMMC_REGIDX_RFC 0x3C 173#define ASTMMC_REGIDX_PLL 0x40 174 175TIME_TABLE_DDR3_1333: 176 .word 0x53503C37 @ 0x010 177 .word 0xF858D47F @ 0x014 178 .word 0x00010000 @ 0x018 179 .word 0x00000000 @ 0x020 180 .word 0x00000000 @ 0x024 181 .word 0x02101C60 @ 0x02C 182 .word 0x00000040 @ 0x030 183 .word 0x00000020 @ 0x214 184 .word 0x02001000 @ 0x2E0 185 .word 0x0C000085 @ 0x2E4 186 .word 0x000BA018 @ 0x2E8 187 .word 0x2CB92104 @ 0x2EC 188 .word 0x07090407 @ 0x2F0 189 .word 0x81000700 @ 0x2F4 190 .word 0x0C400800 @ 0x2F8 191 .word 0x7F5E3A27 @ tRFC 192 .word 0x00005B80 @ PLL 193TIME_TABLE_DDR3_1600: 194 .word 0x64604D38 @ 0x010 195 .word 0x29690599 @ 0x014 196 .word 0x00000300 @ 0x018 197 .word 0x00000000 @ 0x020 198 .word 0x00000000 @ 0x024 199 .word 0x02181E70 @ 0x02C 200 .word 0x00000040 @ 0x030 201 .word 0x00000024 @ 0x214 202 .word 0x02001300 @ 0x2E0 203 .word 0x0E0000A0 @ 0x2E4 204 .word 0x000E001B @ 0x2E8 205 .word 0x35B8C105 @ 0x2EC 206 .word 0x08090408 @ 0x2F0 207 .word 0x9B000800 @ 0x2F4 208 .word 0x0E400A00 @ 0x2F8 209 .word 0x9971452F @ tRFC 210 .word 0x000071C1 @ PLL 211 212TIME_TABLE_DDR4_1333: 213 .word 0x53503D26 @ 0x010 214 .word 0xE878D87F @ 0x014 215 .word 0x00019000 @ 0x018 216 .word 0x08000000 @ 0x020 217 .word 0x00000400 @ 0x024 218 .word 0x00000200 @ 0x02C 219 .word 0x00000101 @ 0x030 220 .word 0x00000020 @ 0x214 221 .word 0x03002200 @ 0x2E0 222 .word 0x0C000085 @ 0x2E4 223 .word 0x000BA01A @ 0x2E8 224 .word 0x2CB92106 @ 0x2EC 225 .word 0x07060606 @ 0x2F0 226 .word 0x81000700 @ 0x2F4 227 .word 0x0C400800 @ 0x2F8 228 .word 0x7F5E3A3A @ tRFC 229 .word 0x00005B80 @ PLL 230TIME_TABLE_DDR4_1600: 231 .word 0x63604E37 @ 0x010 232 .word 0xE97AFA99 @ 0x014 233 .word 0x00019000 @ 0x018 234 .word 0x08000000 @ 0x020 235 .word 0x00000400 @ 0x024 236 .word 0x00000410 @ 0x02C 237#ifdef CONFIG_DDR4_SUPPORT_HYNIX 238 .word 0x00000501 @ 0x030 @ ODT = 48 ohm 239#else 240 .word 0x00000101 @ 0x030 @ ODT = 60 ohm 241#endif 242 .word 0x00000024 @ 0x214 243 .word 0x03002900 @ 0x2E0 244 .word 0x0E0000A0 @ 0x2E4 245 .word 0x000E001C @ 0x2E8 246 .word 0x35B8C106 @ 0x2EC 247 .word 0x08080607 @ 0x2F0 248 .word 0x9B000900 @ 0x2F4 249 .word 0x0E400A00 @ 0x2F8 250 .word 0x99714545 @ tRFC 251 .word 0x000071C1 @ PLL 252 253 .macro init_delay_timer 254 ldr r0, =0x1e782024 @ Set Timer3 Reload 255 str r2, [r0] 256 257 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 258 ldr r1, =0x00040000 259 str r1, [r0] 260 261 ldr r0, =0x1e782030 @ Enable Timer3 262 mov r2, #7 263 mov r1, r2, lsl #8 264 str r1, [r0] 265 266 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout 267 .endm 268 269 .macro check_delay_timer 270 ldr r1, [r0] 271 bic r1, r1, #0xFFFBFFFF 272 mov r2, r1, lsr #18 273 cmp r2, #0x01 274 .endm 275 276 .macro clear_delay_timer 277 ldr r0, =0x1e78203C @ Disable Timer3 278 mov r2, #0xF 279 mov r1, r2, lsl #8 280 str r1, [r0] 281 282 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 283 ldr r1, =0x00040000 284 str r1, [r0] 285 .endm 286 287 .macro init_spi_checksum 288 ldr r0, =0x1e620084 289 ldr r1, =0x20010000 290 str r1, [r0] 291 ldr r0, =0x1e62008C 292 ldr r1, =0x20000200 293 str r1, [r0] 294 ldr r0, =0x1e620080 295 ldr r1, =0x0000000D 296 orr r2, r2, r7 297 orr r1, r1, r2, lsl #8 298 and r2, r6, #0xF 299 orr r1, r1, r2, lsl #4 300 str r1, [r0] 301 ldr r0, =0x1e620008 302 ldr r2, =0x00000800 303 .endm 304 305 .macro print_hex_char 306 and r1, r1, #0xF 307 cmp r1, #9 308 addgt r1, r1, #0x37 309 addle r1, r1, #0x30 310 str r1, [r0] 311 .endm 312 313/****************************************************************************** 314 Calibration Macro End 315 ******************************************************************************/ 316 317.globl lowlevel_init 318lowlevel_init: 319 320init_dram: 321 /* save lr */ 322 mov r4, lr 323 324 /******************************************** 325 Initial Reset Procedure : Begin 326 *******************************************/ 327 /* Clear AHB bus lock condition */ 328 ldr r0, =0x1e600000 329 ldr r1, =0xAEED1A03 330 str r1, [r0] 331 ldr r0, =0x1e600084 332 ldr r1, =0x00010000 333 str r1, [r0] 334 add r0, r0, #0x4 335 mov r1, #0x0 336 str r1, [r0] 337 338 ldr r0, =0x1e6e2000 339 ldr r1, =0x1688a8a8 340 str r1, [r0] 341 342 /* Reset again */ 343 ldr r0, =0x1e6e2070 @ check fast reset flag 344 ldr r2, =0x08000000 345 ldr r1, [r0] 346 tst r1, r2 347 beq bypass_first_reset 348 349 ldr r0, =0x1e785010 350 ldr r3, [r0] 351 cmp r3, #0x0 352 beq start_first_reset 353 add r0, r0, #0x04 354 mov r3, #0x77 355 str r3, [r0] 356 ldr r0, =0x1e720004 @ Copy initial strap register to 0x1e720004 357 str r1, [r0] 358 add r0, r0, #0x04 @ Copy initial strap register to 0x1e720008 359 str r1, [r0] 360 add r0, r0, #0x04 @ Copy initial strap register to 0x1e72000c 361 str r1, [r0] 362 ldr r0, =0x1e6e207c @ clear fast reset flag 363 str r2, [r0] 364 ldr r0, =0x1e6e203c @ clear watchdog reset flag 365 ldr r1, [r0] 366 and r1, r1, #0x01 367 str r1, [r0] 368 ldr r0, =0x1e78501c @ restore normal mask setting 369 ldr r1, =0x023FFFF3 @ added 2016.09.06 370 str r1, [r0] 371 b bypass_first_reset 372 373start_first_reset: 374#ifdef ASTMMC_INIT_RESET_MODE_FULL 375 ldr r0, =0x1e785004 376 ldr r1, =0x00000001 377 str r1, [r0] 378 ldr r0, =0x1e785008 379 ldr r1, =0x00004755 380 str r1, [r0] 381 ldr r0, =0x1e78500c @ enable Full reset 382 ldr r1, =0x00000033 383 str r1, [r0] 384#else 385 /***** Clear LPC status : Begin *****/ 386 mov r2, #0 @ set r2 = 0, freezed 387 ldr r0, =0x1e787008 388 mov r1, #0x7 389 str r1, [r0] 390 ldr r0, =0x1e78700c 391 mov r1, #0x3 392 str r1, [r0] 393 ldr r0, =0x1e787020 394 str r2, [r0] 395 ldr r0, =0x1e787034 396 str r2, [r0] 397 ldr r0, =0x1e787004 398 str r2, [r0] 399 ldr r0, =0x1e787010 400 str r2, [r0] 401 ldr r0, =0x1e78701c 402 str r2, [r0] 403 ldr r0, =0x1e787014 @ read clear 404 ldr r1, [r0] 405 ldr r0, =0x1e787018 @ read clear 406 ldr r1, [r0] 407 ldr r0, =0x1e787008 @ read clear 408 ldr r1, [r0] 409 ldr r0, =0x1e78301c @ read clear 410 ldr r1, [r0] 411 ldr r0, =0x1e78d01c @ read clear 412 ldr r1, [r0] 413 ldr r0, =0x1e78e01c @ read clear 414 ldr r1, [r0] 415 ldr r0, =0x1e78f01c @ read clear 416 ldr r1, [r0] 417 ldr r0, =0x1e788020 418 str r2, [r0] 419 ldr r0, =0x1e788034 420 str r2, [r0] 421 ldr r0, =0x1e78800c 422 str r2, [r0] 423 ldr r0, =0x1e789008 424 str r2, [r0] 425 ldr r0, =0x1e789010 426 mov r1, #0x40 427 str r1, [r0] 428 ldr r0, =0x1e789024 @ read clear 429 ldr r1, [r0] 430 ldr r0, =0x1e789028 @ read clear 431 ldr r1, [r0] 432 ldr r0, =0x1e78902c @ read clear 433 ldr r1, [r0] 434 ldr r0, =0x1e789114 @ read clear 435 ldr r1, [r0] 436 ldr r0, =0x1e789124 @ read clear 437 ldr r1, [r0] 438 ldr r0, =0x1e78903c 439 str r2, [r0] 440 ldr r0, =0x1e789040 441 str r2, [r0] 442 ldr r0, =0x1e789044 443 str r2, [r0] 444 ldr r0, =0x1e78911c 445 str r2, [r0] 446 ldr r0, =0x1e78912c 447 ldr r1, =0x200 448 str r1, [r0] 449 ldr r0, =0x1e789104 450 ldr r1, =0xcc00 451 str r1, [r0] 452 ldr r0, =0x1e789108 453 str r2, [r0] 454 ldr r0, =0x1e78910c 455 ldr r1, =0x1f0 456 str r1, [r0] 457 ldr r0, =0x1e789170 458 str r2, [r0] 459 ldr r0, =0x1e789174 460 str r2, [r0] 461 ldr r0, =0x1e7890a0 462 ldr r1, =0xff00 463 str r1, [r0] 464 ldr r0, =0x1e7890a4 465 str r2, [r0] 466 ldr r0, =0x1e789080 467 ldr r1, =0x400 468 str r1, [r0] 469 ldr r0, =0x1e789084 470 ldr r1, =0x0001000f 471 str r1, [r0] 472 ldr r0, =0x1e789088 473 ldr r1, =0x3000fff8 474 str r1, [r0] 475 ldr r0, =0x1e78908c 476 ldr r1, =0xfff8f007 477 str r1, [r0] 478 ldr r0, =0x1e789098 479 ldr r1, =0x00000a30 480 str r1, [r0] 481 ldr r0, =0x1e78909c 482 str r2, [r0] 483 ldr r0, =0x1e789100 484 str r2, [r0] 485 ldr r0, =0x1e789130 486 ldr r1, =0x00000080 487 str r1, [r0] 488 ldr r0, =0x1e789138 489 ldr r1, =0x00010198 490 str r1, [r0] 491 ldr r0, =0x1e789140 492 ldr r1, =0x0000a000 493 str r1, [r0] 494 ldr r0, =0x1e789158 495 ldr r1, =0x00000080 496 str r1, [r0] 497 ldr r0, =0x1e789180 498 ldr r1, =0xb6db1bff 499 str r1, [r0] 500 ldr r0, =0x1e789184 501 str r2, [r0] 502 ldr r0, =0x1e789188 503 str r2, [r0] 504 ldr r0, =0x1e78918c 505 str r2, [r0] 506 ldr r0, =0x1e789190 507 ldr r1, =0x05020100 508 str r1, [r0] 509 ldr r0, =0x1e789194 510 ldr r1, =0x07000706 511 str r1, [r0] 512 ldr r0, =0x1e789198 513 str r2, [r0] 514 ldr r0, =0x1e78919c 515 ldr r1, =0x30 516 str r1, [r0] 517 ldr r0, =0x1e7891a0 518 ldr r1, =0x00008100 519 str r1, [r0] 520 ldr r0, =0x1e7891a4 521 ldr r1, =0x2000 522 str r1, [r0] 523 ldr r0, =0x1e7891a8 524 ldr r1, =0x3ff 525 str r1, [r0] 526 ldr r0, =0x1e7891ac 527 str r2, [r0] 528 ldr r0, =0x1e789240 529 mov r1, #0xff 530 str r1, [r0] 531 ldr r0, =0x1e789244 532 str r1, [r0] 533 ldr r0, =0x1e789248 534 mov r1, #0x80 535 str r1, [r0] 536 ldr r0, =0x1e789250 537 str r2, [r0] 538 ldr r0, =0x1e789254 539 str r2, [r0] 540 /***** Clear LPC status : End *****/ 541 542 ldr r0, =0x1e62009c @ clear software strap flag for doing again after reset 543 ldr r1, =0xAEEDFC20 544 str r1, [r0] 545 ldr r0, =0x1e785004 546 ldr r1, =0x00000001 547 str r1, [r0] 548 ldr r0, =0x1e785008 549 ldr r1, =0x00004755 550 str r1, [r0] 551 ldr r0, =0x1e78501c @ enable full mask of SOC reset 552 ldr r1, =0x03FFFFFF @ added 2016.09.06 553 str r1, [r0] 554 ldr r0, =0x1e78500c @ enable SOC reset 555 ldr r1, =0x00000013 556 str r1, [r0] 557#endif 558wait_first_reset: 559 b wait_first_reset 560 561 /******************************************** 562 Initial Reset Procedure : End 563 *******************************************/ 564 565bypass_first_reset: 566 /* Enable Timer separate clear mode */ 567 ldr r0, =0x1e782038 568 mov r1, #0xAE 569 str r1, [r0] 570 571/* Test - DRAM initial time */ 572 ldr r0, =0x1e78203c 573 ldr r1, =0x0000F000 574 str r1, [r0] 575 576 ldr r0, =0x1e782044 577 ldr r1, =0xFFFFFFFF 578 str r1, [r0] 579 580 ldr r0, =0x1e782030 581 mov r2, #3 582 mov r1, r2, lsl #12 583 str r1, [r0] 584/* Test - DRAM initial time */ 585 586 /*Set Scratch register Bit 7 before initialize*/ 587 ldr r0, =0x1e6e2000 588 ldr r1, =0x1688a8a8 589 str r1, [r0] 590 591 ldr r0, =0x1e6e2040 592 ldr r1, [r0] 593 orr r1, r1, #0x80 594 str r1, [r0] 595 596 /* Change LPC reset source to PERST# when eSPI mode enabled */ 597 ldr r0, =0x1e6e2070 598 ldr r1, [r0] 599 ldr r0, =0x1e6e207c 600 ldr r2, =0x02000000 601 ldr r3, =0x00004000 602 tst r1, r2 603 strne r3, [r0] 604 605 /* Configure USB ports to the correct pin state */ 606 ldr r0, =0x1e6e200c @ enable portA clock 607 ldr r2, =0x00004000 608 ldr r1, [r0] 609 orr r1, r1, r2 610 str r1, [r0] 611 ldr r0, =0x1e6e2090 @ set portA as host mode 612 ldr r1, =0x2000A000 613 str r1, [r0] 614 ldr r0, =0x1e6e2094 @ set portB as host mode 615 ldr r1, =0x00004000 616 str r1, [r0] 617 ldr r0, =0x1e6e2070 618 ldr r2, =0x00800000 619 ldr r1, [r0] 620 tst r1, r2 621 beq bypass_USB_init 622 ldr r0, =0x1e6e207c 623 str r2, [r0] 624 625 /* Delay about 1ms */ 626 clear_delay_timer 627 ldr r2, =0x000003E8 @ Set Timer3 Reload = 1 ms 628 init_delay_timer 629wait_usb_init: 630 check_delay_timer 631 bne wait_usb_init 632 clear_delay_timer 633 /* end delay 1ms */ 634 635 ldr r0, =0x1e6e2070 636 ldr r1, =0x00800000 637 str r1, [r0] 638 639bypass_USB_init: 640 /* Enable AXI_P */ 641 ldr r0, =0x00000016 642 mrc p15, 0, r1, c15, c2, 4 643 mcr p15, 0, r0, c15, c2, 4 644 645/****************************************************************************** 646 Disable WDT2 for 2nd boot function 647 ******************************************************************************/ 648/* 649#ifndef CONFIG_FIRMWARE_2ND_BOOT 650 ldr r0, =0x1e78502c 651 mov r1, #0 652 str r1, [r0] 653#endif 654*/ 655/****************************************************************************** 656 Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function 657 ******************************************************************************/ 658 ldr r0, =0x1e78504c 659 mov r1, #0 660 str r1, [r0] 661 662 ldr r0, =0x1e6e0000 663 ldr r1, =0xFC600309 664 str r1, [r0] 665 666 /* skip SDRAM initialization (will be done in C function) */ 667 b platform_exit 668 669 /* Check Scratch Register Bit 6 */ 670 ldr r0, =0x1e6e2040 671 ldr r1, [r0] 672 bic r1, r1, #0xFFFFFFBF 673 mov r2, r1, lsr #6 674 cmp r2, #0x01 675 beq platform_exit 676 677 /* Disable VGA display */ 678 ldr r0, =0x1e6e202c 679 ldr r1, [r0] 680 orr r1, r1, #0x40 681 str r1, [r0] 682 683 ldr r0, =0x1e6e2070 @ Load strap register 684 ldr r3, [r0] 685 686 /* Set M-PLL */ 687#if defined (CONFIG_DRAM_1333) 688 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330) 689#else 690 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396) 691#if defined (CONFIG_DDR4_SUPPORT_HYNIX) 692 mov r1, r3, lsr #24 @ Check DDR4 693 tst r1, #0x01 694 beq bypass_mpll_hynix_mode_1 695#if defined (CONFIG_DDR4_HYNIX_SET_1536) 696 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384) 697#elif defined (CONFIG_DDR4_HYNIX_SET_1488) 698 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372) 699#else 700 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360) 701#endif 702bypass_mpll_hynix_mode_1: 703#endif 704#endif 705 706 mov r1, r3, lsr #23 @ Check CLKIN = 25MHz 707 tst r1, #0x01 708 beq set_MPLL 709#if defined (CONFIG_DRAM_1333) 710 ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331) 711#else 712 ldr r2, =0x930023E0 @ load PLL parameter for 25Mhz CLKIN (400) 713#if defined (CONFIG_DDR4_SUPPORT_HYNIX) 714 mov r1, r3, lsr #24 @ Check DDR4 715 tst r1, #0x01 716 beq bypass_mpll_hynix_mode_2 717#if defined (CONFIG_DDR4_HYNIX_SET_1536) 718 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (387.5) 719#elif defined (CONFIG_DDR4_HYNIX_SET_1488) 720 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (375) 721#else 722 ldr r2, =0x93002380 @ load PLL parameter for 24Mhz CLKIN (362.5) 723#endif 724bypass_mpll_hynix_mode_2: 725#endif 726#endif 727 ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz) 728 ldr r1, =0x00011320 729 str r1, [r0] 730 731set_MPLL: 732 ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency 733 str r2, [r0] 734 735 clear_delay_timer 736 737 /* Delay about 3ms */ 738 ldr r2, =0x00000BB8 @ Set Timer3 Reload = 3 ms 739 init_delay_timer 740wait_mpll_init: 741 check_delay_timer 742 bne wait_mpll_init 743 clear_delay_timer 744 /* end delay 3ms */ 745 746 /* Reset MMC */ 747reset_mmc: 748 ldr r0, =0x1e78505c 749 ldr r1, =0x00000004 750 str r1, [r0] 751 ldr r0, =0x1e785044 752 ldr r1, =0x00000001 753 str r1, [r0] 754 ldr r0, =0x1e785048 755 ldr r1, =0x00004755 756 str r1, [r0] 757 ldr r0, =0x1e78504c 758 ldr r1, =0x00000013 759 str r1, [r0] 760wait_mmc_reset: 761 ldr r1, [r0] 762 tst r1, #0x02 763 bne wait_mmc_reset 764 765 ldr r0, =0x1e78505c 766 ldr r1, =0x023FFFF3 767 str r1, [r0] 768 ldr r0, =0x1e785044 769 ldr r1, =0x000F4240 770 str r1, [r0] 771 ldr r0, =0x1e785048 772 ldr r1, =0x00004755 773 str r1, [r0] 774 ldr r0, =0x1e785054 775 ldr r1, =0x00000077 776 str r1, [r0] 777 778 ldr r0, =0x1e6e0000 779 ldr r1, =0xFC600309 780wait_mmc_reset_done: 781 str r1, [r0] 782 ldr r2, [r0] 783 cmp r2, #0x1 784 bne wait_mmc_reset_done 785 786 ldr r0, =0x1e6e0034 @ disable MMC request 787 ldr r1, =0x00020000 788 str r1, [r0] 789 790 /* Delay about 10ms */ 791 ldr r2, =0x00002710 @ Set Timer3 Reload = 10 ms 792 init_delay_timer 793wait_ddr_reset: 794 check_delay_timer 795 bne wait_ddr_reset 796 clear_delay_timer 797 /* end delay 10ms */ 798 799/* Debug - UART console message */ 800#ifdef CONFIG_DRAM_UART_TO_UART1 801 ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29 802 ldr r1, =0x10000004 803 str r1, [r0] 804 805 ldr r0, =0x1e6e2084 806 ldr r1, [r0] 807 mov r2, #0xC0 @ Enable pinmux of TXD1/RXD1 808 orr r1, r1, r2, lsl #16 809 str r1, [r0] 810#endif 811 812 ldr r0, =0x1e78400c 813 mov r1, #0x83 814 str r1, [r0] 815 816 ldr r0, =0x1e6e202c 817 ldr r2, [r0] 818 mov r2, r2, lsr #12 819 tst r2, #0x01 820 ldr r0, =0x1e784000 821 moveq r1, #0x0D @ Baudrate 115200 822 movne r1, #0x01 @ Baudrate 115200, div13 823#ifdef CONFIG_DRAM_UART_38400 824 moveq r1, #0x27 @ Baudrate 38400 825 movne r1, #0x03 @ Baudrate 38400 , div13 826#endif 827 str r1, [r0] 828 829 ldr r0, =0x1e784004 830 mov r1, #0x00 831 str r1, [r0] 832 833 ldr r0, =0x1e78400c 834 mov r1, #0x03 835 str r1, [r0] 836 837 ldr r0, =0x1e784008 838 mov r1, #0x07 839 str r1, [r0] 840 841 ldr r0, =0x1e784000 842 mov r1, #0x0D @ '\r' 843 str r1, [r0] 844 mov r1, #0x0A @ '\n' 845 str r1, [r0] 846 mov r1, #0x44 @ 'D' 847 str r1, [r0] 848 mov r1, #0x52 @ 'R' 849 str r1, [r0] 850 mov r1, #0x41 @ 'A' 851 str r1, [r0] 852 mov r1, #0x4D @ 'M' 853 str r1, [r0] 854 mov r1, #0x20 @ ' ' 855 str r1, [r0] 856 mov r1, #0x49 @ 'I' 857 str r1, [r0] 858 mov r1, #0x6E @ 'n' 859 str r1, [r0] 860 mov r1, #0x69 @ 'i' 861 str r1, [r0] 862 mov r1, #0x74 @ 't' 863 str r1, [r0] 864 mov r1, #0x2D @ '-' 865 str r1, [r0] 866 mov r1, #0x56 @ 'V' 867 str r1, [r0] 868 mov r1, #ASTMMC_INIT_VER 869 mov r1, r1, lsr #4 870 print_hex_char 871 mov r1, #ASTMMC_INIT_VER 872 print_hex_char 873 mov r1, #0x2D @ '-' 874 str r1, [r0] 875 ldr r0, =0x1e784014 876wait_print: 877 ldr r1, [r0] 878 tst r1, #0x40 879 beq wait_print 880 ldr r0, =0x1e784000 881 mov r1, #0x44 @ 'D' 882 str r1, [r0] 883 mov r1, #0x44 @ 'D' 884 str r1, [r0] 885 mov r1, #0x52 @ 'R' 886 str r1, [r0] 887/* Debug - UART console message */ 888 889/****************************************************************************** 890 Init DRAM common registers 891 ******************************************************************************/ 892 ldr r0, =0x1e6e0034 @ disable SDRAM reset 893 ldr r1, =0x00020080 894 str r1, [r0] 895 896 ldr r0, =0x1e6e0008 897 ldr r1, =0x2003000F /* VGA */ 898 str r1, [r0] 899 900 ldr r0, =0x1e6e0038 @ disable all DRAM requests except CPU during PHY init 901 ldr r1, =0xFFFFEBFF 902 str r1, [r0] 903 904 ldr r0, =0x1e6e0040 905 ldr r1, =0x88448844 906 str r1, [r0] 907 908 ldr r0, =0x1e6e0044 909 ldr r1, =0x24422288 910 str r1, [r0] 911 912 ldr r0, =0x1e6e0048 913 ldr r1, =0x22222222 914 str r1, [r0] 915 916 ldr r0, =0x1e6e004c 917 ldr r1, =0x22222222 918 str r1, [r0] 919 920 ldr r0, =0x1e6e0050 921 ldr r1, =0x80000000 922 str r1, [r0] 923 924 ldr r1, =0x00000000 925 ldr r0, =0x1e6e0208 @ PHY Setting 926 str r1, [r0] 927 ldr r0, =0x1e6e0218 928 str r1, [r0] 929 ldr r0, =0x1e6e0220 930 str r1, [r0] 931 ldr r0, =0x1e6e0228 932 str r1, [r0] 933 ldr r0, =0x1e6e0230 934 str r1, [r0] 935 ldr r0, =0x1e6e02a8 936 str r1, [r0] 937 ldr r0, =0x1e6e02b0 938 str r1, [r0] 939 940 ldr r0, =0x1e6e0240 941 ldr r1, =0x86000000 942 str r1, [r0] 943 944 ldr r0, =0x1e6e0244 945 ldr r1, =0x00008600 946 str r1, [r0] 947 948 ldr r0, =0x1e6e0248 949 ldr r1, =0x80000000 950 str r1, [r0] 951 952 ldr r0, =0x1e6e024c 953 ldr r1, =0x80808080 954 str r1, [r0] 955 956 /* Check DRAM Type by H/W Trapping */ 957 ldr r0, =0x1e6e2070 958 ldr r1, [r0] 959 ldr r2, =0x01000000 @ bit[24]=1 => DDR4 960 tst r1, r2 961 bne ddr4_init 962 b ddr3_init 963.LTORG 964 965/****************************************************************************** 966 DDR3 Init 967 ******************************************************************************/ 968ddr3_init: 969/* Debug - UART console message */ 970 ldr r0, =0x1e784000 971 mov r1, #0x33 @ '3' 972 str r1, [r0] 973 mov r1, #0x0D @ '\r' 974 str r1, [r0] 975 mov r1, #0x0A @ '\n' 976 str r1, [r0] 977/* Debug - UART console message */ 978 979#if defined (CONFIG_DRAM_1333) 980 adrl r5, TIME_TABLE_DDR3_1333 @ Init DRAM parameter table 981#else 982 adrl r5, TIME_TABLE_DDR3_1600 983#endif 984 985 ldr r0, =0x1e6e0004 986#ifdef CONFIG_DDR3_8GSTACK 987 ldr r1, =0x00000323 @ Init to 8GB stack 988#else 989 ldr r1, =0x00000303 @ Init to 8GB 990#endif 991 str r1, [r0] 992 993 ldr r0, =0x1e6e0010 994 ldr r1, [r5, #ASTMMC_REGIDX_010] 995 str r1, [r0] 996 997 ldr r0, =0x1e6e0014 998 ldr r1, [r5, #ASTMMC_REGIDX_014] 999 str r1, [r0] 1000 1001 ldr r0, =0x1e6e0018 1002 ldr r1, [r5, #ASTMMC_REGIDX_018] 1003 str r1, [r0] 1004 1005 /* DRAM Mode Register Setting */ 1006 ldr r0, =0x1e6e0020 @ MRS_4/6 1007 ldr r1, [r5, #ASTMMC_REGIDX_020] 1008 str r1, [r0] 1009 1010 ldr r0, =0x1e6e0024 @ MRS_5 1011 ldr r1, [r5, #ASTMMC_REGIDX_024] 1012 str r1, [r0] 1013 1014 ldr r0, =0x1e6e002c @ MRS_0/2 1015 ldr r1, [r5, #ASTMMC_REGIDX_02C] 1016 mov r2, #0x1 1017 orr r1, r1, r2, lsl #8 1018 str r1, [r0] 1019 1020 ldr r0, =0x1e6e0030 @ MRS_1/3 1021 ldr r1, [r5, #ASTMMC_REGIDX_030] 1022 str r1, [r0] 1023 1024 /* Start DDR PHY Setting */ 1025 ldr r0, =0x1e6e0200 1026 ldr r1, =0x02492AAE 1027 str r1, [r0] 1028 1029 ldr r0, =0x1e6e0204 1030#ifdef CONFIG_DDR3_8GSTACK 1031 ldr r1, =0x10001001 1032#else 1033 ldr r1, =0x00001001 1034#endif 1035 str r1, [r0] 1036 1037 ldr r0, =0x1e6e020c 1038 ldr r1, =0x55E00B0B 1039 str r1, [r0] 1040 1041 ldr r0, =0x1e6e0210 1042 ldr r1, =0x20000000 1043 str r1, [r0] 1044 1045 ldr r0, =0x1e6e0214 1046 ldr r1, [r5, #ASTMMC_REGIDX_214] 1047 str r1, [r0] 1048 1049 ldr r0, =0x1e6e02e0 1050 ldr r1, [r5, #ASTMMC_REGIDX_2E0] 1051 str r1, [r0] 1052 1053 ldr r0, =0x1e6e02e4 1054 ldr r1, [r5, #ASTMMC_REGIDX_2E4] 1055 str r1, [r0] 1056 1057 ldr r0, =0x1e6e02e8 1058 ldr r1, [r5, #ASTMMC_REGIDX_2E8] 1059 str r1, [r0] 1060 1061 ldr r0, =0x1e6e02ec 1062 ldr r1, [r5, #ASTMMC_REGIDX_2EC] 1063 str r1, [r0] 1064 1065 ldr r0, =0x1e6e02f0 1066 ldr r1, [r5, #ASTMMC_REGIDX_2F0] 1067 str r1, [r0] 1068 1069 ldr r0, =0x1e6e02f4 1070 ldr r1, [r5, #ASTMMC_REGIDX_2F4] 1071 str r1, [r0] 1072 1073 ldr r0, =0x1e6e02f8 1074 ldr r1, [r5, #ASTMMC_REGIDX_2F8] 1075 str r1, [r0] 1076 1077 ldr r0, =0x1e6e0290 1078 ldr r1, =0x00100008 1079 str r1, [r0] 1080 1081 ldr r0, =0x1e6e02c0 1082 ldr r1, =0x00000006 1083 str r1, [r0] 1084 1085 /* Controller Setting */ 1086 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1087 ldr r1, =0x00000005 1088 str r1, [r0] 1089 1090 ldr r0, =0x1e6e0034 1091 ldr r1, =0x00020091 1092 str r1, [r0] 1093 1094/* Debug - UART console message */ 1095 ldr r0, =0x1e784000 1096 mov r1, #0x30 @ '0' 1097 str r1, [r0] 1098/* Debug - UART console message */ 1099 1100 ldr r0, =0x1e6e0120 1101 mov r1, #0x00 1102 str r1, [r0] 1103 b ddr_phy_init_process 1104 1105ddr3_phyinit_done: 1106 1107 /******************************************** 1108 Check Read training margin 1109 ********************************************/ 1110 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window 1111 ldr r1, [r0] 1112 ldr r2, =0x150 1113 bic r0, r1, #0xFF000000 1114 bic r0, r0, #0x00FF0000 1115 cmp r0, r2 1116 blt ddr_test_fail 1117 mov r0, r1, lsr #16 1118 cmp r0, r2 1119 blt ddr_test_fail 1120 1121 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window 1122 ldr r1, [r0] 1123 ldr r2, =0x90 1124 bic r0, r1, #0x0000FF00 1125 cmp r0, r2 1126 blt ddr_test_fail 1127 mov r0, r1, lsr #8 1128 cmp r0, r2 1129 blt ddr_test_fail 1130 /*******************************************/ 1131 1132/* Debug - UART console message */ 1133 ldr r0, =0x1e784000 1134 mov r1, #0x31 @ '1' 1135 str r1, [r0] 1136/* Debug - UART console message */ 1137 1138 ldr r0, =0x1e6e000c 1139 ldr r1, =0x00000040 1140 str r1, [r0] 1141 1142#ifdef CONFIG_DDR3_8GSTACK 1143 ldr r0, =0x1e6e0028 1144 ldr r1, =0x00000025 1145 str r1, [r0] 1146 1147 ldr r0, =0x1e6e0028 1148 ldr r1, =0x00000027 1149 str r1, [r0] 1150 1151 ldr r0, =0x1e6e0028 1152 ldr r1, =0x00000023 1153 str r1, [r0] 1154 1155 ldr r0, =0x1e6e0028 1156 ldr r1, =0x00000021 1157 str r1, [r0] 1158#endif 1159 1160 ldr r0, =0x1e6e0028 1161 ldr r1, =0x00000005 1162 str r1, [r0] 1163 1164 ldr r0, =0x1e6e0028 1165 ldr r1, =0x00000007 1166 str r1, [r0] 1167 1168 ldr r0, =0x1e6e0028 1169 ldr r1, =0x00000003 1170 str r1, [r0] 1171 1172 ldr r0, =0x1e6e0028 1173 ldr r1, =0x00000011 1174 str r1, [r0] 1175 1176 ldr r0, =0x1e6e000c 1177 ldr r1, =0x00005C41 1178 str r1, [r0] 1179 1180 ldr r0, =0x1e6e0034 1181 ldr r2, =0x70000000 1182ddr3_check_dllrdy: 1183 ldr r1, [r0] 1184 tst r1, r2 1185 bne ddr3_check_dllrdy 1186 1187 ldr r0, =0x1e6e000c 1188#ifdef CONFIG_DRAM_EXT_TEMP 1189 ldr r1, =0x42AA2F81 1190#else 1191 ldr r1, =0x42AA5C81 1192#endif 1193 str r1, [r0] 1194 1195 ldr r0, =0x1e6e0034 1196 ldr r1, =0x0001AF93 1197 str r1, [r0] 1198 1199 ldr r0, =0x1e6e0120 @ VGA Compatible Mode 1200 ldr r1, [r5, #ASTMMC_REGIDX_PLL] 1201 str r1, [r0] 1202 1203 b Calibration_End 1204.LTORG 1205/****************************************************************************** 1206 End DDR3 Init 1207 ******************************************************************************/ 1208/****************************************************************************** 1209 DDR4 Init 1210 ******************************************************************************/ 1211ddr4_init: 1212/* Debug - UART console message */ 1213 ldr r0, =0x1e784000 1214 mov r1, #0x34 @ '4' 1215 str r1, [r0] 1216 mov r1, #0x0D @ '\r' 1217 str r1, [r0] 1218 mov r1, #0x0A @ '\n' 1219 str r1, [r0] 1220/* Debug - UART console message */ 1221 1222#if defined (CONFIG_DRAM_1333) 1223 adrl r5, TIME_TABLE_DDR4_1333 @ Init DRAM parameter table 1224#else 1225 adrl r5, TIME_TABLE_DDR4_1600 1226#endif 1227 1228 ldr r0, =0x1e6e0004 1229#ifdef CONFIG_DDR4_4GX8 1230 ldr r1, =0x00002313 @ Init to 8GB 1231#else 1232 ldr r1, =0x00000313 @ Init to 8GB 1233#endif 1234 str r1, [r0] 1235 1236 ldr r0, =0x1e6e0010 1237 ldr r1, [r5, #ASTMMC_REGIDX_010] 1238 str r1, [r0] 1239 1240 ldr r0, =0x1e6e0014 1241 ldr r1, [r5, #ASTMMC_REGIDX_014] 1242 str r1, [r0] 1243 1244 ldr r0, =0x1e6e0018 1245 ldr r1, [r5, #ASTMMC_REGIDX_018] 1246 str r1, [r0] 1247 1248 /* DRAM Mode Register Setting */ 1249 ldr r0, =0x1e6e0020 @ MRS_4/6 1250 ldr r1, [r5, #ASTMMC_REGIDX_020] 1251 str r1, [r0] 1252 1253 ldr r0, =0x1e6e0024 @ MRS_5 1254 ldr r1, [r5, #ASTMMC_REGIDX_024] 1255 str r1, [r0] 1256 1257 ldr r0, =0x1e6e002c @ MRS_0/2 1258 ldr r1, [r5, #ASTMMC_REGIDX_02C] 1259 mov r2, #0x1 1260 orr r1, r1, r2, lsl #8 1261 str r1, [r0] 1262 1263 ldr r0, =0x1e6e0030 @ MRS_1/3 1264 ldr r1, [r5, #ASTMMC_REGIDX_030] 1265 str r1, [r0] 1266 1267 /* Start DDR PHY Setting */ 1268 ldr r0, =0x1e6e0200 1269 ldr r1, =0x42492AAE 1270 str r1, [r0] 1271 1272 ldr r0, =0x1e6e0204 1273 ldr r1, =0x09002800 1274 str r1, [r0] 1275 1276 ldr r0, =0x1e6e020c 1277 ldr r1, =0x55E00B0B 1278 str r1, [r0] 1279 1280 ldr r0, =0x1e6e0210 1281 ldr r1, =0x20000000 1282 str r1, [r0] 1283 1284 ldr r0, =0x1e6e0214 1285 ldr r1, [r5, #ASTMMC_REGIDX_214] 1286 str r1, [r0] 1287 1288 ldr r0, =0x1e6e02e0 1289 ldr r1, [r5, #ASTMMC_REGIDX_2E0] 1290 str r1, [r0] 1291 1292 ldr r0, =0x1e6e02e4 1293 ldr r1, [r5, #ASTMMC_REGIDX_2E4] 1294 str r1, [r0] 1295 1296 ldr r0, =0x1e6e02e8 1297 ldr r1, [r5, #ASTMMC_REGIDX_2E8] 1298 str r1, [r0] 1299 1300 ldr r0, =0x1e6e02ec 1301 ldr r1, [r5, #ASTMMC_REGIDX_2EC] 1302 str r1, [r0] 1303 1304 ldr r0, =0x1e6e02f0 1305 ldr r1, [r5, #ASTMMC_REGIDX_2F0] 1306 str r1, [r0] 1307 1308 ldr r0, =0x1e6e02f4 1309 ldr r1, [r5, #ASTMMC_REGIDX_2F4] 1310 str r1, [r0] 1311 1312 ldr r0, =0x1e6e02f8 1313 ldr r1, [r5, #ASTMMC_REGIDX_2F8] 1314 str r1, [r0] 1315 1316 ldr r0, =0x1e6e0290 1317 ldr r1, =0x00100008 1318 str r1, [r0] 1319 1320 ldr r0, =0x1e6e02c4 1321 ldr r1, =0x3C183C3C 1322 str r1, [r0] 1323 1324 ldr r0, =0x1e6e02c8 1325 ldr r1, =0x00631E0E 1326 str r1, [r0] 1327 1328 ldr r0, =0x1e6e0034 1329 ldr r1, =0x0001A991 1330 str r1, [r0] 1331 1332/* Debug - UART console message */ 1333 ldr r0, =0x1e784000 1334 mov r1, #0x30 @ '0' 1335 str r1, [r0] 1336/* Debug - UART console message */ 1337 1338 /******************************************** 1339 Set Ron value to manual mode 1340 Target to fix DDR CK Vix issue 1341 Set Ron_pu = 0, Ron_pd = trained value 1342 *******************************************/ 1343#ifdef ASTMMC_DDR4_MANUAL_RPU 1344 ldr r0, =0x1e6e02c0 1345 ldr r1, =0x00001806 1346 str r1, [r0] 1347 ldr r0, =0x1e6e02cc 1348 ldr r1, =0x00005050 1349 str r1, [r0] 1350 ldr r0, =0x1e6e0120 1351 mov r1, #0x04 1352 str r1, [r0] 1353 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1354 mov r1, #0x05 1355 str r1, [r0] 1356 b ddr_phy_init_process 1357 1358ddr4_ron_phyinit_done: 1359 1360 ldr r0, =0x1e6e0300 @ read calibrated Ron_pd 1361 ldr r3, [r0] 1362 bic r3, r3, #0xFFFFFF0F 1363 ldr r0, =0x1e6e0240 1364 ldr r1, [r0] 1365 bic r1, r1, #0xFF000000 1366 mov r2, #ASTMMC_DDR4_MANUAL_RPU 1367 orr r1, r1, r2, lsl #24 1368#ifdef ASTMMC_DDR4_MANUAL_RPD 1369 mov r2, #ASTMMC_DDR4_MANUAL_RPD 1370 orr r1, r1, r2, lsl #28 1371#else 1372 orr r1, r1, r3, lsl #24 1373#endif 1374 orr r1, r1, #0x02 1375 str r1, [r0] 1376 1377 ldr r0, =0x1e6e0060 @ Reset PHY 1378 mov r1, #0x00 1379 str r1, [r0] 1380#endif 1381 /******************************************** 1382 PHY Vref Scan 1383 r6 : recorded vref value 1384 r7 : max read eye pass window 1385 r8 : passcnt 1386 r9 : CBRtest result 1387 r10: loopcnt 1388 r11: free 1389 ********************************************/ 1390 ldr r0, =0x1e720000 @ retry count 1391 mov r1, #0x5 1392 str r1, [r0] 1393ddr4_vref_phy_cal_start: 1394 mov r7, #0x0 1395 mov r8, #0x0 1396 mov r10, #0x3F 1397 1398 ldr r0, =0x1e720000 1399 ldr r1, [r0] 1400 subs r1, r1, #0x01 1401 beq ddr_test_fail 1402 str r1, [r0] 1403 1404 ldr r0, =0x1e6e0120 1405 ldr r1, =0x00000001 1406 str r1, [r0] 1407 1408/* Debug - UART console message */ 1409 ldr r0, =0x1e784000 1410 mov r1, #0x61 @ 'a' 1411 str r1, [r0] 1412/* Debug - UART console message */ 1413 1414 ldr r0, =0x1e6e02c0 1415 ldr r1, =0x00001C06 1416 str r1, [r0] 1417 1418ddr4_vref_phy_loop: 1419 ldr r0, =0x1e6e0060 1420 ldr r1, =0x00000000 1421 str r1, [r0] 1422 1423 add r10, r10, #0x01 1424 cmp r10, #0x80 1425 beq ddr4_vref_phy_test_fail @ no valid margin and retry 1426 1427 ldr r0, =0x1e6e02cc 1428 orr r1, r10, r10, lsl #8 1429 str r1, [r0] 1430 1431 ldr r0, =0x1e6e0060 1432 ldr r1, =0x00000005 1433 str r1, [r0] 1434 b ddr_phy_init_process 1435 1436ddr4_vref_phy_phyinit_done: 1437 1438 b cbr_test_start 1439 1440ddr4_vref_phy_cbrtest_done: 1441 ldr r0, =0x1e6e03d0 @ read eye pass window 1442 ldr r1, [r0] 1443 ldr r0, =0x1e720000 1444 add r0, r0, r10, lsl #2 1445 str r1, [r0] 1446 cmp r9, #0x01 1447 bne ddr4_vref_phy_test_fail 1448 add r8, r8, #0x01 1449 ldr r0, =0x1e6e03d0 @ read eye pass window 1450 ldr r1, [r0] 1451 mov r2, r1, lsr #8 @ r2 = DQH 1452 and r1, r1, #0xFF @ r1 = DQL 1453 cmp r1, r2 1454 movgt r1, r2 @ r1 = smaller one 1455 cmp r1, r7 1456 movgt r6, r10 1457 movgt r7, r1 1458 b ddr4_vref_phy_loop 1459 1460ddr4_vref_phy_test_fail: 1461 cmp r8, #0x0 1462 bne ddr4_vref_phy_loop_end 1463 cmp r10, #0x80 1464 beq ddr4_vref_phy_cal_start 1465 b ddr4_vref_phy_loop 1466 1467ddr4_vref_phy_loop_end: 1468 cmp r8, #16 @ check phyvref margin >= 16 1469 blt ddr_test_fail 1470 ldr r0, =0x1e6e02cc 1471 orr r1, r6, r6, lsl #8 1472 str r1, [r0] 1473 ldr r0, =0x1e720010 1474 orr r1, r6, r7, lsl #8 1475 orr r1, r1, r8, lsl #16 1476 str r1, [r0] 1477 1478 /******************************************** 1479 DDR Vref Scan 1480 r6 : min 1481 r7 : max 1482 r8 : passcnt 1483 r9 : CBRtest result 1484 r10: loopcnt 1485 r11: free 1486 ********************************************/ 1487 ldr r0, =0x1e720000 @ retry count 1488 mov r1, #0x5 1489 str r1, [r0] 1490ddr4_vref_ddr_cal_start: 1491 mov r6, #0xFF 1492 mov r7, #0x0 1493 mov r8, #0x0 1494 mov r10, #0x0 1495 1496 ldr r0, =0x1e720000 1497 ldr r1, [r0] 1498 subs r1, r1, #0x01 1499 beq ddr_test_fail 1500 str r1, [r0] 1501 1502 ldr r0, =0x1e6e0120 1503 ldr r1, =0x00000002 1504 str r1, [r0] 1505 1506/* Debug - UART console message */ 1507 ldr r0, =0x1e784000 1508 mov r1, #0x62 @ 'b' 1509 str r1, [r0] 1510/* Debug - UART console message */ 1511 1512ddr4_vref_ddr_loop: 1513 ldr r0, =0x1e6e0060 1514 ldr r1, =0x00000000 1515 str r1, [r0] 1516 1517 add r10, r10, #0x01 1518 cmp r10, #0x40 1519 beq ddr4_vref_ddr_test_fail @ no valid margin and retry 1520 1521 ldr r0, =0x1e6e02c0 1522 mov r1, #0x06 1523 orr r1, r1, r10, lsl #8 1524 str r1, [r0] 1525 1526 ldr r0, =0x1e6e0060 1527 ldr r1, =0x00000005 1528 str r1, [r0] 1529 b ddr_phy_init_process 1530 1531ddr4_vref_ddr_phyinit_done: 1532 1533 b cbr_test_start 1534 1535ddr4_vref_ddr_cbrtest_done: 1536 cmp r9, #0x01 1537 bne ddr4_vref_ddr_test_fail 1538 add r8, r8, #0x01 1539 cmp r6, r10 1540 movgt r6, r10 1541 cmp r7, r10 1542 movlt r7, r10 1543 b ddr4_vref_ddr_loop 1544 1545ddr4_vref_ddr_test_fail: 1546 cmp r8, #0x0 1547 bne ddr4_vref_ddr_loop_end 1548 cmp r10, #0x40 1549 beq ddr4_vref_ddr_cal_start 1550 b ddr4_vref_ddr_loop 1551 1552ddr4_vref_ddr_loop_end: 1553 ldr r0, =0x1e6e0060 1554 ldr r1, =0x00000000 1555 str r1, [r0] 1556 1557 cmp r8, #16 @ check ddrvref margin >= 16 1558 blt ddr_test_fail 1559 ldr r0, =0x1e6e02c0 1560 add r1, r6, r7 1561 add r1, r1, #0x01 1562 mov r2, r1, lsr #1 1563 mov r1, r2, lsl #8 1564 orr r1, r1, #0x06 1565 str r1, [r0] 1566 ldr r0, =0x1e720014 1567 orr r1, r6, r7, lsl #8 1568 orr r1, r1, r8, lsl #16 1569 str r1, [r0] 1570 1571/* Debug - UART console message */ 1572 ldr r0, =0x1e784000 1573 mov r1, #0x63 @ 'c' 1574 str r1, [r0] 1575/* Debug - UART console message */ 1576 1577 ldr r0, =0x1e6e0120 1578 ldr r1, =0x00000003 1579 str r1, [r0] 1580 1581 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1582 ldr r1, =0x00000005 1583 str r1, [r0] 1584 b ddr_phy_init_process 1585 1586ddr4_phyinit_done: 1587 1588 /******************************************** 1589 Check Read training margin 1590 ********************************************/ 1591 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window 1592 ldr r1, [r0] 1593 ldr r2, =0x150 1594 bic r0, r1, #0xFF000000 1595 bic r0, r0, #0x00FF0000 1596 cmp r0, r2 1597 blt ddr_test_fail 1598 mov r0, r1, lsr #16 1599 cmp r0, r2 1600 blt ddr_test_fail 1601 1602 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window 1603 ldr r1, [r0] 1604 ldr r2, =0x90 1605 bic r0, r1, #0x0000FF00 1606 cmp r0, r2 1607 blt ddr_test_fail 1608 mov r0, r1, lsr #8 1609 cmp r0, r2 1610 blt ddr_test_fail 1611 /*******************************************/ 1612 1613 /*******************************************/ 1614/* Debug - UART console message */ 1615 ldr r0, =0x1e784000 1616 mov r1, #0x31 @ '1' 1617 str r1, [r0] 1618/* Debug - UART console message */ 1619 1620 ldr r0, =0x1e6e000c 1621#ifdef CONFIG_DRAM_EXT_TEMP 1622 ldr r1, =0x42AA2F81 1623#else 1624 ldr r1, =0x42AA5C81 1625#endif 1626 str r1, [r0] 1627 1628 ldr r0, =0x1e6e0034 1629 ldr r1, =0x0001AF93 1630 str r1, [r0] 1631 1632 ldr r0, =0x1e6e0120 @ VGA Compatible Mode 1633 ldr r1, [r5, #ASTMMC_REGIDX_PLL] 1634 str r1, [r0] 1635 1636 b Calibration_End 1637 1638.LTORG 1639/****************************************************************************** 1640 End DDR4 Init 1641 ******************************************************************************/ 1642/****************************************************************************** 1643 Global Process 1644 ******************************************************************************/ 1645 /******************************************** 1646 DDRPHY Init Process 1647 ********************************************/ 1648ddr_phy_init_process: 1649 clear_delay_timer 1650 /* Wait DDR PHY init done - timeout 300 ms */ 1651 ldr r2, =0x000493E0 @ Set Timer3 Reload = 300 ms 1652 init_delay_timer 1653 ldr r3, =0x1e6e0060 1654ddr_phy_init: 1655 check_delay_timer 1656 beq ddr_phy_init_timeout 1657 ldr r1, [r3] 1658 tst r1, #0x01 1659 bne ddr_phy_init 1660 1661 /* Check DDR PHY init status */ 1662 ldr r0, =0x1e6e0300 1663 ldr r2, =0x000A0000 1664 ldr r1, [r0] 1665 tst r1, r2 1666 beq ddr_phy_init_success 1667 1668ddr_phy_init_timeout: 1669 ldr r0, =0x1e6e0060 @ Reset PHY 1670 mov r1, #0x00 1671 str r1, [r0] 1672 1673/* Debug - UART console message */ 1674 ldr r0, =0x1e784000 1675 mov r1, #0x2E @ '.' 1676 str r1, [r0] 1677/* Debug - UART console message */ 1678 1679 clear_delay_timer 1680 /* Delay about 10us */ 1681 ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us 1682 init_delay_timer 1683ddr_phy_init_delay_0: 1684 check_delay_timer 1685 bne ddr_phy_init_delay_0 1686 clear_delay_timer 1687 /* end delay 10us */ 1688 1689 ldr r0, =0x1e6e0060 @ Fire PHY Init 1690 mov r1, #0x05 1691 str r1, [r0] 1692 b ddr_phy_init_process 1693 1694ddr_phy_init_success: 1695 clear_delay_timer 1696 ldr r0, =0x1e6e0060 1697 mov r1, #0x06 1698 str r1, [r0] 1699 1700 ldr r0, =0x1e6e0120 1701 ldr r1, [r0] 1702 cmp r1, #0 1703 beq ddr3_phyinit_done 1704 cmp r1, #1 1705 beq ddr4_vref_phy_phyinit_done 1706 cmp r1, #2 1707 beq ddr4_vref_ddr_phyinit_done 1708#ifdef ASTMMC_DDR4_MANUAL_RPU 1709 cmp r1, #4 1710 beq ddr4_ron_phyinit_done 1711#endif 1712 b ddr4_phyinit_done 1713 1714 /******************************************** 1715 CBRTest 1716 ********************************************/ 1717cbr_test_start: 1718 ldr r0, =0x1e6e000c 1719 ldr r1, =0x00005C01 1720 str r1, [r0] 1721 ldr r0, =0x1e6e0074 1722 ldr r1, =0x0000FFFF @ test size = 64KB 1723 str r1, [r0] 1724 ldr r0, =0x1e6e007c 1725 ldr r1, =0xFF00FF00 1726 str r1, [r0] 1727 1728cbr_test_single: 1729 ldr r0, =0x1e6e0070 1730 ldr r1, =0x00000000 1731 str r1, [r0] 1732 ldr r1, =0x00000085 1733 str r1, [r0] 1734 ldr r3, =0x3000 1735 ldr r11, =0x50000 1736cbr_wait_engine_idle_0: 1737 subs r11, r11, #1 1738 beq cbr_test_fail 1739 ldr r2, [r0] 1740 tst r2, r3 @ D[12] = idle bit 1741 beq cbr_wait_engine_idle_0 1742 1743 ldr r0, =0x1e6e0070 @ read fail bit status 1744 ldr r3, =0x2000 1745 ldr r2, [r0] 1746 tst r2, r3 @ D[13] = fail bit 1747 bne cbr_test_fail 1748 1749cbr_test_burst: 1750 mov r1, #0x00 @ initialize loop index, r1 is loop index 1751cbr_test_burst_loop: 1752 ldr r0, =0x1e6e0070 1753 ldr r2, =0x00000000 1754 str r2, [r0] 1755 mov r2, r1, lsl #3 1756 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) 1757 str r2, [r0] 1758 ldr r3, =0x3000 1759 ldr r11, =0x20000 1760cbr_wait_engine_idle_1: 1761 subs r11, r11, #1 1762 beq cbr_test_fail 1763 ldr r2, [r0] 1764 tst r2, r3 @ D[12] = idle bit 1765 beq cbr_wait_engine_idle_1 1766 1767 ldr r0, =0x1e6e0070 @ read fail bit status 1768 ldr r3, =0x2000 1769 ldr r2, [r0] 1770 tst r2, r3 @ D[13] = fail bit 1771 bne cbr_test_fail 1772 1773 add r1, r1, #1 @ increase the test mode index 1774 cmp r1, #0x04 @ test 4 modes 1775 bne cbr_test_burst_loop 1776 1777 ldr r0, =0x1e6e0070 1778 ldr r1, =0x00000000 1779 str r1, [r0] 1780 mov r9, #0x1 1781 b cbr_test_pattern_end @ CBRTest() return(1) 1782 1783cbr_test_fail: 1784 ldr r0, =0x1e6e0070 1785 ldr r1, =0x00000000 1786 str r1, [r0] 1787 mov r9, #0x0 @ CBRTest() return(0) 1788 1789cbr_test_pattern_end: 1790 ldr r0, =0x1e6e000c 1791 ldr r1, =0x00000000 1792 str r1, [r0] 1793 ldr r0, =0x1e6e0120 1794 ldr r1, [r0] 1795 cmp r1, #1 1796 beq ddr4_vref_phy_cbrtest_done 1797 b ddr4_vref_ddr_cbrtest_done 1798 1799.LTORG 1800/****************************************************************************** 1801 Other features configuration 1802 *****************************************************************************/ 1803Calibration_End: 1804 /******************************* 1805 Check DRAM Size 1806 1Gb : 0x80000000 ~ 0x87FFFFFF 1807 2Gb : 0x80000000 ~ 0x8FFFFFFF 1808 4Gb : 0x80000000 ~ 0x9FFFFFFF 1809 8Gb : 0x80000000 ~ 0xBFFFFFFF 1810 *******************************/ 1811 ldr r0, =0x1e6e0004 1812 ldr r6, [r0] 1813 bic r6, r6, #0x00000003 @ record MCR04 1814 ldr r7, [r5, #ASTMMC_REGIDX_RFC] 1815 1816check_dram_size: 1817 ldr r0, =0xA0100000 1818 ldr r1, =0x41424344 1819 str r1, [r0] 1820 ldr r0, =0x90100000 1821 ldr r1, =0x35363738 1822 str r1, [r0] 1823 ldr r0, =0x88100000 1824 ldr r1, =0x292A2B2C 1825 str r1, [r0] 1826 ldr r0, =0x80100000 1827 ldr r1, =0x1D1E1F10 1828 str r1, [r0] 1829 ldr r0, =0xA0100000 1830 ldr r1, =0x41424344 1831 ldr r2, [r0] 1832 cmp r2, r1 @ == 8Gbit 1833 orreq r6, r6, #0x03 1834 moveq r7, r7, lsr #24 1835 mov r3, #0x38 @ '8' 1836 beq check_dram_size_end 1837 ldr r0, =0x90100000 1838 ldr r1, =0x35363738 1839 ldr r2, [r0] 1840 cmp r2, r1 @ == 4Gbit 1841 orreq r6, r6, #0x02 1842 moveq r7, r7, lsr #16 1843 mov r3, #0x34 @ '4' 1844 beq check_dram_size_end 1845 ldr r0, =0x88100000 1846 ldr r1, =0x292A2B2C 1847 ldr r2, [r0] 1848 cmp r2, r1 @ == 2Gbit 1849 orreq r6, r6, #0x01 1850 moveq r7, r7, lsr #8 1851 mov r3, #0x32 @ '2' 1852 beq check_dram_size_end 1853 mov r3, #0x31 @ '1' 1854 1855check_dram_size_end: 1856 ldr r0, =0x1e6e0004 1857 str r6, [r0] 1858 ldr r0, =0x1e6e0014 1859 ldr r1, [r0] 1860 bic r1, r1, #0x000000FF 1861 and r7, r7, #0xFF 1862 orr r1, r1, r7 1863 str r1, [r0] 1864 1865 /* Version Number */ 1866 ldr r0, =0x1e6e0004 1867 ldr r1, [r0] 1868 mov r2, #ASTMMC_INIT_VER 1869 orr r1, r1, r2, lsl #20 1870 str r1, [r0] 1871 1872 ldr r0, =0x1e6e0088 1873 ldr r1, =ASTMMC_INIT_DATE 1874 str r1, [r0] 1875 1876/* Debug - UART console message */ 1877 ldr r0, =0x1e784000 1878 mov r1, #0x2D @ '-' 1879 str r1, [r0] 1880 str r3, [r0] 1881 mov r1, #0x47 @ 'G' 1882 str r1, [r0] 1883 mov r1, #0x62 @ 'b' 1884 str r1, [r0] 1885 mov r1, #0x2D @ '-' 1886 str r1, [r0] 1887/* Debug - UART console message */ 1888 1889 /* Enable DRAM Cache */ 1890 ldr r0, =0x1e6e0004 1891 ldr r1, [r0] 1892 mov r2, #1 1893 orr r2, r1, r2, lsl #12 1894 str r2, [r0] 1895 ldr r3, =0x00080000 1896dram_cache_init: 1897 ldr r2, [r0] 1898 tst r2, r3 1899 beq dram_cache_init 1900 mov r2, #1 1901 orr r1, r1, r2, lsl #10 1902 str r1, [r0] 1903 1904 /* Set DRAM requests threshold */ 1905 ldr r0, =0x1e6e001c 1906 ldr r1, =0x00000008 1907 str r1, [r0] 1908 ldr r0, =0x1e6e0038 1909 ldr r1, =0xFFFFFF00 1910 str r1, [r0] 1911 1912 /******************************************** 1913 DDRTest 1914 ********************************************/ 1915ddr_test_start: 1916 ldr r0, =0x1e6e0074 1917 ldr r1, =0x0000FFFF @ test size = 64KB 1918 str r1, [r0] 1919 ldr r0, =0x1e6e007c 1920 ldr r1, =0xFF00FF00 1921 str r1, [r0] 1922 1923ddr_test_burst: 1924 mov r1, #0x00 @ initialize loop index, r1 is loop index 1925ddr_test_burst_loop: 1926 ldr r0, =0x1e6e0070 1927 ldr r2, =0x00000000 1928 str r2, [r0] 1929 mov r2, r1, lsl #3 1930 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) 1931 str r2, [r0] 1932 ldr r3, =0x3000 1933 ldr r11, =0x20000 1934ddr_wait_engine_idle_1: 1935 subs r11, r11, #1 1936 beq ddr_test_fail 1937 ldr r2, [r0] 1938 tst r2, r3 @ D[12] = idle bit 1939 beq ddr_wait_engine_idle_1 1940 1941 ldr r0, =0x1e6e0070 @ read fail bit status 1942 ldr r3, =0x2000 1943 ldr r2, [r0] 1944 tst r2, r3 @ D[13] = fail bit 1945 bne ddr_test_fail 1946 1947 add r1, r1, #1 @ increase the test mode index 1948 cmp r1, #0x01 @ test 1 modes 1949 bne ddr_test_burst_loop 1950 1951 ldr r0, =0x1e6e0070 1952 ldr r1, =0x00000000 1953 str r1, [r0] 1954 b set_scratch @ CBRTest() return(1) 1955 1956ddr_test_fail: 1957/* Debug - UART console message */ 1958 ldr r0, =0x1e784000 1959 mov r1, #0x46 @ 'F' 1960 str r1, [r0] 1961 mov r1, #0x61 @ 'a' 1962 str r1, [r0] 1963 mov r1, #0x69 @ 'i' 1964 str r1, [r0] 1965 mov r1, #0x6C @ 'l' 1966 str r1, [r0] 1967 mov r1, #0x0D @ '\r' 1968 str r1, [r0] 1969 mov r1, #0x0A @ '\n' 1970 str r1, [r0] 1971 ldr r0, =0x1e784014 1972wait_print_0: 1973 ldr r1, [r0] 1974 tst r1, #0x40 1975 beq wait_print_0 1976/* Debug - UART console message */ 1977 b reset_mmc 1978 1979set_scratch: 1980 /*Set Scratch register Bit 6 after ddr initial finished */ 1981 ldr r0, =0x1e6e2040 1982 ldr r1, [r0] 1983 orr r1, r1, #0x41 1984 str r1, [r0] 1985 1986/* Debug - UART console message */ 1987 ldr r0, =0x1e784000 1988 mov r1, #0x44 @ 'D' 1989 str r1, [r0] 1990 mov r1, #0x6F @ 'o' 1991 str r1, [r0] 1992 mov r1, #0x6E @ 'n' 1993 str r1, [r0] 1994 mov r1, #0x65 @ 'e' 1995 str r1, [r0] 1996 mov r1, #0x0D @ '\r' 1997 str r1, [r0] 1998 mov r1, #0x0A @ '\n' 1999 str r1, [r0] 2000/* Debug - UART console message */ 2001 2002 /* Enable VGA display */ 2003 ldr r0, =0x1e6e202c 2004 ldr r1, [r0] 2005 bic r1, r1, #0x40 2006 str r1, [r0] 2007 2008/* Debug - UART console message */ 2009 /* Print PHY timing information */ 2010 ldr r0, =0x1e784014 2011wait_print_1: 2012 ldr r1, [r0] 2013 tst r1, #0x40 2014 beq wait_print_1 2015 2016 ldr r0, =0x1e784000 2017 mov r1, #0x52 @ 'R' 2018 str r1, [r0] 2019 mov r1, #0x65 @ 'e' 2020 str r1, [r0] 2021 mov r1, #0x61 @ 'a' 2022 str r1, [r0] 2023 mov r1, #0x64 @ 'd' 2024 str r1, [r0] 2025 mov r1, #0x20 @ ' ' 2026 str r1, [r0] 2027 mov r1, #0x6D @ 'm' 2028 str r1, [r0] 2029 mov r1, #0x61 @ 'a' 2030 str r1, [r0] 2031 mov r1, #0x72 @ 'r' 2032 str r1, [r0] 2033 mov r1, #0x67 @ 'g' 2034 str r1, [r0] 2035 mov r1, #0x69 @ 'i' 2036 str r1, [r0] 2037 mov r1, #0x6E @ 'n' 2038 str r1, [r0] 2039 mov r1, #0x2D @ '-' 2040 str r1, [r0] 2041 mov r1, #0x44 @ 'D' 2042 str r1, [r0] 2043 mov r1, #0x4C @ 'L' 2044 str r1, [r0] 2045 mov r1, #0x3A @ ':' 2046 str r1, [r0] 2047 2048 ldr r0, =0x1e784014 2049wait_print_2: 2050 ldr r1, [r0] 2051 tst r1, #0x40 2052 beq wait_print_2 2053 2054 ldr r7, =0x000001FE @ divide by 510 2055 mov r8, #10 @ multiply by 10 2056 mov r9, #0 @ record violation 2057 ldr r0, =0x1e6e0004 2058 ldr r1, [r0] 2059 tst r1, #0x10 @ bit[4]=1 => DDR4 2060 movne r10, #0x9A @ DDR4 min = 0x99 (0.30) 2061 moveq r10, #0xB3 @ DDR3 min = 0xB3 (0.35) 2062print_DQL_eye_margin: 2063 ldr r0, =0x1e6e03d0 2064 ldr r2, [r0] 2065 and r2, r2, #0xFF 2066 cmp r2, r10 @ check violation 2067 movlt r9, #1 2068 ldr r0, =0x1e784000 2069 mov r1, #0x30 @ '0' 2070 str r1, [r0] 2071 mov r1, #0x2E @ '.' 2072 str r1, [r0] 2073 mov r3, #0x4 @ print 4 digits 2074print_DQL_div_loop: 2075 mul r2, r8, r2 2076 cmp r2, r7 2077 blt print_DQL_div_0 2078 mov r6, #0x0 2079print_DQL_div_digit: 2080 sub r2, r2, r7 2081 add r6, r6, #0x1 2082 cmp r2, r7 2083 bge print_DQL_div_digit 2084 b print_DQL_div_n 2085 2086print_DQL_div_0: 2087 mov r1, #0x30 @ '0' 2088 str r1, [r0] 2089 b print_DQL_next 2090print_DQL_div_n: 2091 add r1, r6, #0x30 @ print n 2092 str r1, [r0] 2093print_DQL_next: 2094 subs r3, r3, #1 2095 beq print_DQH_eye_margin 2096 cmp r2, #0x0 2097 beq print_DQH_eye_margin 2098 b print_DQL_div_loop 2099 2100print_DQH_eye_margin: 2101 mov r1, #0x2F @ '/' 2102 str r1, [r0] 2103 mov r1, #0x44 @ 'D' 2104 str r1, [r0] 2105 mov r1, #0x48 @ 'H' 2106 str r1, [r0] 2107 mov r1, #0x3A @ ':' 2108 str r1, [r0] 2109 2110 ldr r0, =0x1e784014 2111wait_print_3: 2112 ldr r1, [r0] 2113 tst r1, #0x40 2114 beq wait_print_3 2115 2116 ldr r0, =0x1e6e03d0 2117 ldr r2, [r0] 2118 mov r2, r2, lsr #8 2119 and r2, r2, #0xFF 2120 cmp r2, r10 @ check violation 2121 movlt r9, #1 2122 ldr r0, =0x1e784000 2123 mov r1, #0x30 @ '0' 2124 str r1, [r0] 2125 mov r1, #0x2E @ '.' 2126 str r1, [r0] 2127 mov r3, #0x4 @ print 4 digits 2128print_DQH_div_loop: 2129 mul r2, r8, r2 2130 cmp r2, r7 2131 blt print_DQH_div_0 2132 mov r6, #0x0 2133print_DQH_div_digit: 2134 sub r2, r2, r7 2135 add r6, r6, #0x1 2136 cmp r2, r7 2137 bge print_DQH_div_digit 2138 b print_DQH_div_n 2139 2140print_DQH_div_0: 2141 mov r1, #0x30 @ '0' 2142 str r1, [r0] 2143 b print_DQH_next 2144print_DQH_div_n: 2145 add r1, r6, #0x30 @ print n 2146 str r1, [r0] 2147print_DQH_next: 2148 subs r3, r3, #1 2149 beq print_DQ_eye_margin_last 2150 cmp r2, #0x0 2151 beq print_DQ_eye_margin_last 2152 b print_DQH_div_loop 2153 2154print_DQ_eye_margin_last: 2155 mov r1, #0x20 @ ' ' 2156 str r1, [r0] 2157 mov r1, #0x43 @ 'C' 2158 str r1, [r0] 2159 mov r1, #0x4B @ 'K' 2160 str r1, [r0] 2161 2162 ldr r0, =0x1e6e0004 2163 ldr r1, [r0] 2164 tst r1, #0x10 @ bit[4]=1 => DDR4 2165 movne r10, #0x30 @ DDR4 min = 0.30 2166 moveq r10, #0x35 @ DDR4 min = 0.35 2167 2168 ldr r0, =0x1e784014 2169wait_print_4: 2170 ldr r1, [r0] 2171 tst r1, #0x40 2172 beq wait_print_4 2173 2174 ldr r0, =0x1e784000 2175 mov r1, #0x20 @ ' ' 2176 str r1, [r0] 2177 mov r1, #0x28 @ '(' 2178 str r1, [r0] 2179 mov r1, #0x6D @ 'm' 2180 str r1, [r0] 2181 mov r1, #0x69 @ 'i' 2182 str r1, [r0] 2183 mov r1, #0x6E @ 'n' 2184 str r1, [r0] 2185 mov r1, #0x3A @ ':' 2186 str r1, [r0] 2187 mov r1, #0x30 @ '0' 2188 str r1, [r0] 2189 mov r1, #0x2E @ '.' 2190 str r1, [r0] 2191 mov r1, #0x33 @ '3' 2192 str r1, [r0] 2193 str r10, [r0] 2194 mov r1, #0x29 @ ')' 2195 str r1, [r0] 2196 2197 cmp r9, #0 2198 beq print_DQ_margin_last 2199 mov r1, #0x20 @ ' ' 2200 str r1, [r0] 2201 ldr r0, =0x1e784014 2202wait_print_5: 2203 ldr r1, [r0] 2204 tst r1, #0x40 2205 beq wait_print_5 2206 2207 ldr r0, =0x1e784000 2208 mov r1, #0x57 @ 'W' 2209 str r1, [r0] 2210 mov r1, #0x61 @ 'a' 2211 str r1, [r0] 2212 mov r1, #0x72 @ 'r' 2213 str r1, [r0] 2214 mov r1, #0x6E @ 'n' 2215 str r1, [r0] 2216 mov r1, #0x69 @ 'i' 2217 str r1, [r0] 2218 mov r1, #0x6E @ 'n' 2219 str r1, [r0] 2220 mov r1, #0x67 @ 'g' 2221 str r1, [r0] 2222 mov r1, #0x3A @ ':' 2223 str r1, [r0] 2224 mov r1, #0x20 @ ' ' 2225 str r1, [r0] 2226 mov r1, #0x4D @ 'M' 2227 str r1, [r0] 2228 mov r1, #0x61 @ 'a' 2229 str r1, [r0] 2230 mov r1, #0x72 @ 'r' 2231 str r1, [r0] 2232 mov r1, #0x67 @ 'g' 2233 str r1, [r0] 2234 mov r1, #0x69 @ 'i' 2235 str r1, [r0] 2236 mov r1, #0x6E @ 'n' 2237 str r1, [r0] 2238 ldr r0, =0x1e784014 2239wait_print_6: 2240 ldr r1, [r0] 2241 tst r1, #0x40 2242 beq wait_print_6 2243 ldr r0, =0x1e784000 2244 mov r1, #0x20 @ ' ' 2245 str r1, [r0] 2246 mov r1, #0x74 @ 't' 2247 str r1, [r0] 2248 mov r1, #0x6F @ 'o' 2249 str r1, [r0] 2250 mov r1, #0x6F @ 'o' 2251 str r1, [r0] 2252 mov r1, #0x20 @ ' ' 2253 str r1, [r0] 2254 mov r1, #0x73 @ 's' 2255 str r1, [r0] 2256 mov r1, #0x6D @ 'm' 2257 str r1, [r0] 2258 mov r1, #0x61 @ 'a' 2259 str r1, [r0] 2260 mov r1, #0x6C @ 'l' 2261 str r1, [r0] 2262 mov r1, #0x6C @ 'l' 2263 str r1, [r0] 2264 2265print_DQ_margin_last: 2266 mov r1, #0x0D @ '\r' 2267 str r1, [r0] 2268 mov r1, #0x0A @ '\n' 2269 str r1, [r0] 2270/* Debug - UART console message */ 2271 2272platform_exit: 2273#ifdef CONFIG_DRAM_ECC 2274 ldr r0, =0x1e6e0004 2275 ldr r2, =0x00000880 @ add cache range control, 2016.09.02 2276 ldr r1, [r0] 2277 orr r1, r1, r2 2278 str r1, [r0] 2279 2280 ldr r0, =0x1e6e0054 2281 ldr r1, =CONFIG_DRAM_ECC_SIZE /* ECC protected memory size */ 2282 str r1, [r0] 2283 2284 ldr r0, =0x1e6e007C 2285 ldr r1, =0x00000000 2286 str r1, [r0] 2287 ldr r0, =0x1e6e0074 2288 str r1, [r0] 2289 2290 ldr r0, =0x1e6e0070 2291 ldr r1, =0x00000221 2292 str r1, [r0] 2293 2294 ldr r2, =0x00001000 2295ECC_Init_Flag: 2296 ldr r1, [r0] 2297 tst r1, r2 @ D[12] = 1, Done 2298 beq ECC_Init_Flag 2299 2300 ldr r1, =0x00000000 2301 str r1, [r0] 2302 2303 ldr r0, =0x1e6e0050 2304 ldr r1, =0x80000000 2305 str r1, [r0] 2306 2307 ldr r0, =0x1e6e0050 2308 ldr r1, =0x00000000 2309 str r1, [r0] 2310 2311 ldr r0, =0x1e6e0070 2312 ldr r1, =0x00000400 @ Enable ECC auto-scrubbing 2313 str r1, [r0] 2314#endif 2315 2316/****************************************************************************** 2317 SPI Timing Calibration 2318 ******************************************************************************/ 2319 mov r2, #0x0 2320 mov r6, #0x0 2321 mov r7, #0x0 2322 init_spi_checksum 2323spi_checksum_wait_0: 2324 ldr r1, [r0] 2325 tst r1, r2 2326 beq spi_checksum_wait_0 2327 ldr r0, =0x1e620090 2328 ldr r5, [r0] @ record golden checksum 2329 ldr r0, =0x1e620080 2330 mov r1, #0x0 2331 str r1, [r0] 2332 2333 ldr r0, =0x1e620010 @ set to fast read mode 2334 ldr r1, =0x000B0041 2335 str r1, [r0] 2336 2337 ldr r6, =0x00F7E6D0 @ Init spiclk loop 2338 mov r8, #0x0 @ Init delay record 2339 2340spi_cbr_next_clkrate: 2341 mov r6, r6, lsr #0x4 2342 cmp r6, #0x0 2343 beq spi_cbr_end 2344 2345 mov r7, #0x0 @ Init delay loop 2346 mov r8, r8, lsl #4 2347 2348spi_cbr_next_delay_s: 2349 mov r2, #0x8 2350 init_spi_checksum 2351spi_checksum_wait_1: 2352 ldr r1, [r0] 2353 tst r1, r2 2354 beq spi_checksum_wait_1 2355 ldr r0, =0x1e620090 2356 ldr r2, [r0] @ read checksum 2357 ldr r0, =0x1e620080 2358 mov r1, #0x0 2359 str r1, [r0] 2360 cmp r2, r5 2361 bne spi_cbr_next_delay_e 2362 2363 mov r2, #0x0 2364 init_spi_checksum 2365spi_checksum_wait_2: 2366 ldr r1, [r0] 2367 tst r1, r2 2368 beq spi_checksum_wait_2 2369 ldr r0, =0x1e620090 2370 ldr r2, [r0] @ read checksum 2371 ldr r0, =0x1e620080 2372 mov r1, #0x0 2373 str r1, [r0] 2374 cmp r2, r5 2375 bne spi_cbr_next_delay_e 2376 2377 orr r8, r8, r7 @ record passed delay 2378 b spi_cbr_next_clkrate 2379 2380spi_cbr_next_delay_e: 2381 add r7, r7, #0x1 2382 cmp r7, #0x6 2383 blt spi_cbr_next_delay_s 2384 b spi_cbr_next_clkrate 2385 2386spi_cbr_end: 2387 ldr r0, =0x1e620094 2388 str r8, [r0] 2389 ldr r0, =0x1e620010 2390 mov r1, #0x0 2391 str r1, [r0] 2392 2393/****************************************************************************** 2394 Miscellaneous Setting 2395 ******************************************************************************/ 2396 /* Set UART DMA as AHB high priority master */ 2397 ldr r0, =0x1e600000 2398 ldr r1, =0xAEED1A03 2399 str r1, [r0] 2400 2401 ldr r0, =0x1e600080 2402 ldr r2, =0x100 2403 ldr r1, [r0] 2404 orr r1, r1, r2 2405 str r1, [r0] 2406 2407 /* Enable UART3/4 clock and disable LHCLK */ 2408 ldr r0, =0x1e6e200c 2409 ldr r1, [r0] 2410 ldr r2, =0xF9FFFFFF 2411 and r1, r1, r2 2412 ldr r2, =0x10000000 2413 orr r1, r1, r2 2414 str r1, [r0] 2415 2416 ldr r0, =0x1e6e2008 @ Set Video ECLK phase 2417 ldr r1, [r0] 2418 ldr r2, =0x0ffffff3 2419 and r1, r1, r2 2420 str r1, [r0] 2421 2422 ldr r0, =0x1e6e2004 @ Enable JTAG Master, solve ARM stucked by JTAG issue 2423 ldr r1, [r0] 2424 bic r1, r1, #0x00400000 2425 str r1, [r0] 2426 2427/****************************************************************************** 2428 Configure MAC timing 2429 ******************************************************************************/ 2430 /* Enable D2PLL and set to 250MHz */ 2431 ldr r0, =0x1e6e213c 2432 ldr r1, =0x00000585 @ Reset D2PLL 2433 str r1, [r0] 2434 2435 ldr r0, =0x1e6e202c 2436 ldr r1, [r0] 2437 bic r1, r1, #0x10 @ Enable D2PLL 2438 ldr r2, =0x00200000 @ Set CRT = 40MHz 2439 orr r1, r1, r2 2440 str r1, [r0] 2441 2442 ldr r2, =0x8E00A17C @ Set to 250MHz 2443 2444 ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz 2445 ldr r1, [r0] 2446 mov r1, r1, lsr #23 2447 tst r1, #0x01 2448 beq set_D2PLL 2449 ldr r2, =0x8E00A177 2450 2451set_D2PLL: 2452 ldr r0, =0x1e6e201c 2453 str r2, [r0] 2454 ldr r0, =0x1e6e213c @ Enable D2PLL 2455 ldr r1, =0x00000580 2456 str r1, [r0] 2457 2458 ldr r0, =0x1e6e204c 2459 ldr r1, [r0] 2460 bic r1, r1, #0xFF0000 2461 ldr r2, =0x00040000 @ Set divider ratio 2462 orr r1, r1, r2 2463 str r1, [r0] 2464 2465 ldr r0, =0x1e6e2048 @ Set MAC interface delay timing = 1G 2466 ldr r1, =0x80082208 @ Select internal 125MHz 2467 str r1, [r0] 2468 ldr r0, =0x1e6e20b8 @ Set MAC interface delay timing = 100M 2469 str r1, [r0] 2470 ldr r0, =0x1e6e20bc @ Set MAC interface delay timing = 10M 2471 str r1, [r0] 2472 2473 ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock 2474 ldr r1, [r0] 2475 mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10 2476 tst r1, #0xC0 2477 movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6 2478 ldr r0, =0x1e6e2008 2479 ldr r1, [r0] 2480 bic r1, r1, #0x00070000 2481 orr r1, r1, r2, lsl #16 2482 str r1, [r0] 2483 2484 ldr r0, =0x1e6e21dc @ Set MAC duty 2485 ldr r1, =0x00666400 2486 str r1, [r0] 2487 2488 ldr r0, =0x1e6e2090 @ Enable MAC interface pull low 2489 ldr r1, [r0] 2490 bic r1, r1, #0x0000F000 2491 bic r1, r1, #0x20000000 @ Set USB portA as Device mode 2492 str r1, [r0] 2493 2494/* Test - DRAM initial time */ 2495 ldr r0, =0x1e782040 2496 ldr r1, [r0] 2497 ldr r0, =0xFFFFFFFF 2498 sub r1, r0, r1 2499 ldr r0, =0x1e6e008c 2500 str r1, [r0] 2501 ldr r0, =0x1e78203c 2502 ldr r1, =0x0000F000 2503 str r1, [r0] 2504/* Test - DRAM initial time */ 2505 2506 ldr r0, =0x1e6e0000 @ disable MMC password 2507 mov r1, #0x0 2508 str r1, [r0] 2509 2510 /* Disable Timer separate mode */ 2511 ldr r0, =0x1e782038 2512 ldr r1, =0xEA 2513 str r1, [r0] 2514 2515 /* restore lr */ 2516 mov lr, r4 2517 2518 /* back to arch calling code */ 2519 mov pc, lr 2520 2521