1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * AST25x0 DDR3/DDR4 SDRAM controller initialization sequence 17 * 18 * Gary Hsu, <gary_hsu@aspeedtech.com> 19 * 20 * Version : 18 21 * Release date: 2017.10.27 22 * 23 * Priority of fix item: 24 * [P1] = critical 25 * [P2] = nice to have 26 * [P3] = minor 27 * 28 * Change List : 29 * V2 |2014.07.25 : 1.[P1] Modify HPLL config sequence 30 * V2 |2014.07.30 : 1.[P1] Modify DDR3 AC parameters table 31 * | 2.[P1] Turn on ZQCS mode 32 * V2 |2014.08.13 : 1.[P1] Add disable XDMA 33 * V2 |2014.09.09 : 1.[P1] Disable CKE dynamic power down 34 * V2 |2014.10.31 : 1.[P2] Enable VGA wide screen support (SCU40[0]=1) 35 * V2 |2015.03.26 : 1.[P1] Revise AC timing table 36 * | 2.[P1] Add check code to bypass A0 patch 37 * | 3.[P1] Add MPLL parameter of A1 38 * | 4.[P1] Set X-DMA into VGA memory domain 39 * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init 40 * | 2.[P1] Set MCR1C & MCR38 41 * V3 |2015.05.13 : 1.[P1] Modify DDR4 PHY Vref training algorithm 42 * | 2.[P2] Enable CKE dynamic power down 43 * V4 |2015.06.15 : 1.[P1] Add MAC timing setting 44 * V5 |2015.07.09 : 1.[P1] Modify MHCLK divider ratio 45 * | 2.[P2] Add DDR read margin report 46 * V6 |2015.08.13 : 1.[P3] Disable MMC password before exit 47 * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition 48 * V7 |2015.09.18 : 1.[P1] Clear AHB bus lock condition at power up time 49 * | 2.[P1] Add reset MMC controller to solve init DRAM again during VGA ON 50 * V7 |2015.09.22 : 1.[P1] Add watchdog full reset for resolving reset incomplete issue at fast reset condition 51 * | 2.[P1] Add DRAM stress test after train complete, and redo DRAM initial if stress fail 52 * | 3.[P2] Enable JTAG master mode 53 * | 4.[P2] Add DDR4 Vref trainig retry timeout 54 * V8 |2015.11.02 : 1.[P2] Clear software strap flag before doing watchdog full reset 55 * |2015.12.10 : 1.[P1] Add USB PHY initial code 56 * |2016.01.27 : 1.[P3] Modify the first reset from full chip reset to SOC reset 57 * | 2.[P3] Remove HPLL/MPLL patch code for revision A0 58 * | 3.[P2] Move the reset_mmc code to be after MPLL initialized 59 * V9 |2016.02.19 : 1.[P3] Remove definition "CONFIG_FIRMWARE_2ND_BOOT" 60 * V10|2016.04.21 : 1.[P1] Add USB PHY initial code - port B, to prevent wrong state on USB pins 61 * V11|2016.05.10 : 1.[P3] Add DRAM Extended temperature range support 62 * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled 63 * |2016.07.12 : 2.[P1] Modify DDR4 read path ODT from 60 ohm to 48 ohm, at address 0x1e6e0204 64 * | : 3.[P1] Modify DDR4 Ron calibration to manual mode to fix Vix issue, set Ron_pu = 0 65 * | : 4.[P2] Modify read timing margin report policy, change DDR4 min value from 0.35 to 0.3. Add "Warning" while violated. 66 * V13|2016.08.29 : 1.[P3] Add option to route debug message output port from UART5 to UART1 67 * |2016.09.02 : 2.[P2] Add range control for cache function when ECC enabled 68 * |2016.09.06 : 3.[P1] Enable full mask setting for first SOC reset, since the coverage of original default setting is not enough 69 * V14|2016.10.25 : 1.[P2] Change Ron manual calibration to default OFF, customer can enable it to do fine-tuning of the Vix issue 70 * |2016.11.07 : 2.[P3] Add log information of DDR4 PHY Vref training 71 * V15|2017.04.06 : 1.[P1] Modify USB portA initial sequence, this is to prevent DMA lock condition of USB Virtual Hub device for some chips. 72 * |2017.04.13 : 2.[P2] Add initial sequence for LPC controller 73 * V16|2017.06.15 : 1.[P1] Add margin check/retry for DDR4 Vref training margin. 74 * |2017.06.15 : 2.[P1] Add margin check/retry for DDR3/DDR4 read timing training margin. 75 * |2017.06.19 : 3.[P2] Add initial sequence for LPC controller 76 * |2017.06.19 : 4.[P2] Add initial full-chip reset option 77 * |2017.06.19 : 5.[P3] Add 10ms delay after DDR reset 78 * V17|2017.09.25 : 1.[P1] Modify DDR4 side ODT value from 60ohm to 48ohm. 79 * |2017.09.25 : 2.[P1] Add Hynix DDR4 frequency slow down option. 80 * V18|2017.10.26 : 1.[P3] Include the modification of DDR4 side ODT value in V17 into the option of Hynix DDR4 configuration. 81 * |2017.10.26 : 2.[P2] Enhance initial sequence for LPC controller 82 * Note: Read timing report is only a reference, it is not a solid rule for stability. 83 * 84 * Optional define variable 85 * 1. DRAM Speed // 86 * CONFIG_DRAM_1333 // 87 * CONFIG_DRAM_1600 // (default) 88 * 2. ECC Function enable 89 * CONFIG_DRAM_ECC // define to enable ECC function 90 * CONFIG_DRAM_ECC_SIZE // define the ECC protected memory size 91 * 3. UART5 message output // 92 * CONFIG_DRAM_UART_38400 // set the UART baud rate to 38400, default is 115200 93 * CONFIG_DRAM_UART_TO_UART1 // route UART5 to UART port1 94 * 4. DRAM Type 95 * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die 96 * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part 97 * 5. Firmware 2nd boot flash 98 * CONFIG_FIRMWARE_2ND_BOOT (Removed) 99 * 6. Enable DRAM extended temperature range mode 100 * CONFIG_DRAM_EXT_TEMP 101 * 7. Select WDT_Full mode for power up initial reset 102 * ASTMMC_INIT_RESET_MODE_FULL 103 * 8. Hynix DDR4 options 104 * CONFIG_DDR4_SUPPORT_HYNIX // Enable this when Hynix DDR4 included in the BOM 105 * CONFIG_DDR4_HYNIX_SET_1536 106 * CONFIG_DDR4_HYNIX_SET_1488 107 * CONFIG_DDR4_HYNIX_SET_1440 // Default 108 ****************************************************************************** 109 */ 110 111#include <config.h> 112#include <version.h> 113 114/****************************************************************************** 115 r4 : return program counter 116 r5 : DDR speed timing table base address 117 Free registers: 118 r0, r1, r2, r3, r6, r7, r8, r9, r10, r11 119 ******************************************************************************/ 120#define ASTMMC_INIT_VER 0x12 @ 8bit verison number 121#define ASTMMC_INIT_DATE 0x20171027 @ Release date 122 123/****************************************************************************** 124 BMC side DDR IO driving manual mode fine-tuning, used to improve CK/CKN Vix violation. 125 Default disabled, the driver setting is hardware auto tuned. 126 127 ASTMMC_DDR4_MANUAL_RPU | ASTMMC_DDR4_MANUAL_RPD 128 -----------------------+----------------------- 129 No | x : manual mode disabled 130 Yes | No : enable Rpu manual setting 131 Yes | Yes : enable Rpu/Rpd manual setting 132 ******************************************************************************/ 133//#define ASTMMC_DDR4_MANUAL_RPU 0x0 @ 0x0-0xF, larger value means weaker driving 134//#define ASTMMC_DDR4_MANUAL_RPD 0x0 @ 0x0-0xF, larger value means stronger driving 135 136/****************************************************************************** 137 Select initial reset mode as WDT_Full 138 WDT_Full is a more complete reset mode than WDT_SOC. 139 But if FW has other initial code executed before platform.S, then it should use WDT_SOC mode. 140 Use WDT_Full may clear the initial result of prior initial code. 141 ******************************************************************************/ 142//#define ASTMMC_INIT_RESET_MODE_FULL 143 144/****************************************************************************** 145 There is a compatibility issue for Hynix DDR4 SDRAM. 146 Hynix DDR4 SDRAM is more weak on noise margin compared to Micron and Samsung DDR4. 147 To well support Hynix DDR4, it requlres to slow down the DDR4 operating frequency 148 from 1600Mbps to 1536/1488/1440 Mbps. The target frequency that can be used depends 149 on the MB layout. Customer can find the appropriate frequency for their products. 150 Below are the new defined parameters for the Hynix DDR4 supporting. 151 ******************************************************************************/ 152#define CONFIG_DDR4_SUPPORT_HYNIX @ Enable this when Hynix DDR4 included in the BOM 153//#define CONFIG_DDR4_HYNIX_SET_1536 154//#define CONFIG_DDR4_HYNIX_SET_1488 155#define CONFIG_DDR4_HYNIX_SET_1440 156 157#define ASTMMC_REGIDX_010 0x00 158#define ASTMMC_REGIDX_014 0x04 159#define ASTMMC_REGIDX_018 0x08 160#define ASTMMC_REGIDX_020 0x0C 161#define ASTMMC_REGIDX_024 0x10 162#define ASTMMC_REGIDX_02C 0x14 163#define ASTMMC_REGIDX_030 0x18 164#define ASTMMC_REGIDX_214 0x1C 165#define ASTMMC_REGIDX_2E0 0x20 166#define ASTMMC_REGIDX_2E4 0x24 167#define ASTMMC_REGIDX_2E8 0x28 168#define ASTMMC_REGIDX_2EC 0x2C 169#define ASTMMC_REGIDX_2F0 0x30 170#define ASTMMC_REGIDX_2F4 0x34 171#define ASTMMC_REGIDX_2F8 0x38 172#define ASTMMC_REGIDX_RFC 0x3C 173#define ASTMMC_REGIDX_PLL 0x40 174 175TIME_TABLE_DDR3_1333: 176 .word 0x53503C37 @ 0x010 177 .word 0xF858D47F @ 0x014 178 .word 0x00010000 @ 0x018 179 .word 0x00000000 @ 0x020 180 .word 0x00000000 @ 0x024 181 .word 0x02101C60 @ 0x02C 182 .word 0x00000040 @ 0x030 183 .word 0x00000020 @ 0x214 184 .word 0x02001000 @ 0x2E0 185 .word 0x0C000085 @ 0x2E4 186 .word 0x000BA018 @ 0x2E8 187 .word 0x2CB92104 @ 0x2EC 188 .word 0x07090407 @ 0x2F0 189 .word 0x81000700 @ 0x2F4 190 .word 0x0C400800 @ 0x2F8 191 .word 0x7F5E3A27 @ tRFC 192 .word 0x00005B80 @ PLL 193TIME_TABLE_DDR3_1600: 194 .word 0x64604D38 @ 0x010 195 .word 0x29690599 @ 0x014 196 .word 0x00000300 @ 0x018 197 .word 0x00000000 @ 0x020 198 .word 0x00000000 @ 0x024 199 .word 0x02181E70 @ 0x02C 200 .word 0x00000040 @ 0x030 201 .word 0x00000024 @ 0x214 202 .word 0x02001300 @ 0x2E0 203 .word 0x0E0000A0 @ 0x2E4 204 .word 0x000E001B @ 0x2E8 205 .word 0x35B8C105 @ 0x2EC 206 .word 0x08090408 @ 0x2F0 207 .word 0x9B000800 @ 0x2F4 208 .word 0x0E400A00 @ 0x2F8 209 .word 0x9971452F @ tRFC 210 .word 0x000071C1 @ PLL 211 212TIME_TABLE_DDR4_1333: 213 .word 0x53503D26 @ 0x010 214 .word 0xE878D87F @ 0x014 215 .word 0x00019000 @ 0x018 216 .word 0x08000000 @ 0x020 217 .word 0x00000400 @ 0x024 218 .word 0x00000200 @ 0x02C 219 .word 0x00000101 @ 0x030 220 .word 0x00000020 @ 0x214 221 .word 0x03002200 @ 0x2E0 222 .word 0x0C000085 @ 0x2E4 223 .word 0x000BA01A @ 0x2E8 224 .word 0x2CB92106 @ 0x2EC 225 .word 0x07060606 @ 0x2F0 226 .word 0x81000700 @ 0x2F4 227 .word 0x0C400800 @ 0x2F8 228 .word 0x7F5E3A3A @ tRFC 229 .word 0x00005B80 @ PLL 230TIME_TABLE_DDR4_1600: 231 .word 0x63604E37 @ 0x010 232 .word 0xE97AFA99 @ 0x014 233 .word 0x00019000 @ 0x018 234 .word 0x08000000 @ 0x020 235 .word 0x00000400 @ 0x024 236 .word 0x00000410 @ 0x02C 237#ifdef CONFIG_DDR4_SUPPORT_HYNIX 238 .word 0x00000501 @ 0x030 @ ODT = 48 ohm 239#else 240 .word 0x00000101 @ 0x030 @ ODT = 60 ohm 241#endif 242 .word 0x00000024 @ 0x214 243 .word 0x03002900 @ 0x2E0 244 .word 0x0E0000A0 @ 0x2E4 245 .word 0x000E001C @ 0x2E8 246 .word 0x35B8C106 @ 0x2EC 247 .word 0x08080607 @ 0x2F0 248 .word 0x9B000900 @ 0x2F4 249 .word 0x0E400A00 @ 0x2F8 250 .word 0x99714545 @ tRFC 251 .word 0x000071C1 @ PLL 252 253 .macro init_delay_timer 254 ldr r0, =0x1e782024 @ Set Timer3 Reload 255 str r2, [r0] 256 257 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 258 ldr r1, =0x00040000 259 str r1, [r0] 260 261 ldr r0, =0x1e782030 @ Enable Timer3 262 mov r2, #7 263 mov r1, r2, lsl #8 264 str r1, [r0] 265 266 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout 267 .endm 268 269 .macro check_delay_timer 270 ldr r1, [r0] 271 bic r1, r1, #0xFFFBFFFF 272 mov r2, r1, lsr #18 273 cmp r2, #0x01 274 .endm 275 276 .macro clear_delay_timer 277 ldr r0, =0x1e78203C @ Disable Timer3 278 mov r2, #0xF 279 mov r1, r2, lsl #8 280 str r1, [r0] 281 282 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR 283 ldr r1, =0x00040000 284 str r1, [r0] 285 .endm 286 287 .macro init_spi_checksum 288 ldr r0, =0x1e620084 289 ldr r1, =0x20010000 290 str r1, [r0] 291 ldr r0, =0x1e62008C 292 ldr r1, =0x20000200 293 str r1, [r0] 294 ldr r0, =0x1e620080 295 ldr r1, =0x0000000D 296 orr r2, r2, r7 297 orr r1, r1, r2, lsl #8 298 and r2, r6, #0xF 299 orr r1, r1, r2, lsl #4 300 str r1, [r0] 301 ldr r0, =0x1e620008 302 ldr r2, =0x00000800 303 .endm 304 305 .macro print_hex_char 306 and r1, r1, #0xF 307 cmp r1, #9 308 addgt r1, r1, #0x37 309 addle r1, r1, #0x30 310 str r1, [r0] 311 .endm 312 313/****************************************************************************** 314 Calibration Macro End 315 ******************************************************************************/ 316 317.globl lowlevel_init 318lowlevel_init: 319 320init_dram: 321 /* save lr */ 322 mov r4, lr 323 324 /******************************************** 325 Initial Reset Procedure : Begin 326 *******************************************/ 327 /* Clear AHB bus lock condition */ 328 ldr r0, =0x1e600000 329 ldr r1, =0xAEED1A03 330 str r1, [r0] 331 ldr r0, =0x1e600084 332 ldr r1, =0x00010000 333 str r1, [r0] 334 add r0, r0, #0x4 335 mov r1, #0x0 336 str r1, [r0] 337 338 ldr r0, =0x1e6e2000 339 ldr r1, =0x1688a8a8 340 str r1, [r0] 341 342 /* Reset again */ 343 ldr r0, =0x1e6e2070 @ check fast reset flag 344 ldr r2, =0x08000000 345 ldr r1, [r0] 346 tst r1, r2 347 beq bypass_first_reset 348 349 ldr r0, =0x1e785010 350 ldr r3, [r0] 351 cmp r3, #0x0 352 beq start_first_reset 353 add r0, r0, #0x04 354 mov r3, #0x77 355 str r3, [r0] 356 ldr r0, =0x1e720004 @ Copy initial strap register to 0x1e720004 357 str r1, [r0] 358 add r0, r0, #0x04 @ Copy initial strap register to 0x1e720008 359 str r1, [r0] 360 add r0, r0, #0x04 @ Copy initial strap register to 0x1e72000c 361 str r1, [r0] 362 ldr r0, =0x1e6e207c @ clear fast reset flag 363 str r2, [r0] 364 ldr r0, =0x1e6e203c @ clear watchdog reset flag 365 ldr r1, [r0] 366 and r1, r1, #0x01 367 str r1, [r0] 368 ldr r0, =0x1e78501c @ restore normal mask setting 369 ldr r1, =0x023FFFF3 @ added 2016.09.06 370 str r1, [r0] 371 b bypass_first_reset 372 373start_first_reset: 374#ifdef ASTMMC_INIT_RESET_MODE_FULL 375 ldr r0, =0x1e785004 376 ldr r1, =0x00000001 377 str r1, [r0] 378 ldr r0, =0x1e785008 379 ldr r1, =0x00004755 380 str r1, [r0] 381 ldr r0, =0x1e78500c @ enable Full reset 382 ldr r1, =0x00000033 383 str r1, [r0] 384#else 385 /***** Clear LPC status : Begin *****/ 386 mov r2, #0 @ set r2 = 0, freezed 387 ldr r0, =0x1e787008 388 mov r1, #0x7 389 str r1, [r0] 390 ldr r0, =0x1e78700c 391 mov r1, #0x3 392 str r1, [r0] 393 ldr r0, =0x1e787020 394 str r2, [r0] 395 ldr r0, =0x1e787034 396 str r2, [r0] 397 ldr r0, =0x1e787004 398 str r2, [r0] 399 ldr r0, =0x1e787010 400 str r2, [r0] 401 ldr r0, =0x1e78701c 402 str r2, [r0] 403 ldr r0, =0x1e787014 @ read clear 404 ldr r1, [r0] 405 ldr r0, =0x1e787018 @ read clear 406 ldr r1, [r0] 407 ldr r0, =0x1e787008 @ read clear 408 ldr r1, [r0] 409 ldr r0, =0x1e78301c @ read clear 410 ldr r1, [r0] 411 ldr r0, =0x1e78d01c @ read clear 412 ldr r1, [r0] 413 ldr r0, =0x1e78e01c @ read clear 414 ldr r1, [r0] 415 ldr r0, =0x1e78f01c @ read clear 416 ldr r1, [r0] 417 ldr r0, =0x1e788020 418 str r2, [r0] 419 ldr r0, =0x1e788034 420 str r2, [r0] 421 ldr r0, =0x1e78800c 422 str r2, [r0] 423 ldr r0, =0x1e789008 424 str r2, [r0] 425 ldr r0, =0x1e789010 426 mov r1, #0x40 427 str r1, [r0] 428 ldr r0, =0x1e789024 @ read clear 429 ldr r1, [r0] 430 ldr r0, =0x1e789028 @ read clear 431 ldr r1, [r0] 432 ldr r0, =0x1e78902c @ read clear 433 ldr r1, [r0] 434 ldr r0, =0x1e789114 @ read clear 435 ldr r1, [r0] 436 ldr r0, =0x1e789124 @ read clear 437 ldr r1, [r0] 438 ldr r0, =0x1e78903c 439 str r2, [r0] 440 ldr r0, =0x1e789040 441 str r2, [r0] 442 ldr r0, =0x1e789044 443 str r2, [r0] 444 ldr r0, =0x1e78911c 445 str r2, [r0] 446 ldr r0, =0x1e78912c 447 ldr r1, =0x200 448 str r1, [r0] 449 ldr r0, =0x1e789104 450 ldr r1, =0xcc00 451 str r1, [r0] 452 ldr r0, =0x1e789108 453 str r2, [r0] 454 ldr r0, =0x1e78910c 455 ldr r1, =0x1f0 456 str r1, [r0] 457 ldr r0, =0x1e789170 458 str r2, [r0] 459 ldr r0, =0x1e789174 460 str r2, [r0] 461 ldr r0, =0x1e7890a0 462 ldr r1, =0xff00 463 str r1, [r0] 464 ldr r0, =0x1e7890a4 465 str r2, [r0] 466 ldr r0, =0x1e789080 467 ldr r1, =0x400 468 str r1, [r0] 469 ldr r0, =0x1e789084 470 ldr r1, =0x0001000f 471 str r1, [r0] 472 ldr r0, =0x1e789088 473 ldr r1, =0x3000fff8 474 str r1, [r0] 475 ldr r0, =0x1e78908c 476 ldr r1, =0xfff8f007 477 str r1, [r0] 478 ldr r0, =0x1e789098 479 ldr r1, =0x00000a30 480 str r1, [r0] 481 ldr r0, =0x1e78909c 482 str r2, [r0] 483 ldr r0, =0x1e789100 484 str r2, [r0] 485 ldr r0, =0x1e789130 486 ldr r1, =0x00000080 487 str r1, [r0] 488 ldr r0, =0x1e789138 489 ldr r1, =0x00010198 490 str r1, [r0] 491 ldr r0, =0x1e789140 492 ldr r1, =0x0000a000 493 str r1, [r0] 494 ldr r0, =0x1e789158 495 ldr r1, =0x00000080 496 str r1, [r0] 497 ldr r0, =0x1e789180 498 ldr r1, =0xb6db1bff 499 str r1, [r0] 500 ldr r0, =0x1e789184 501 str r2, [r0] 502 ldr r0, =0x1e789188 503 str r2, [r0] 504 ldr r0, =0x1e78918c 505 str r2, [r0] 506 ldr r0, =0x1e789190 507 ldr r1, =0x05020100 508 str r1, [r0] 509 ldr r0, =0x1e789194 510 ldr r1, =0x07000706 511 str r1, [r0] 512 ldr r0, =0x1e789198 513 str r2, [r0] 514 ldr r0, =0x1e78919c 515 ldr r1, =0x30 516 str r1, [r0] 517 ldr r0, =0x1e7891a0 518 ldr r1, =0x00008100 519 str r1, [r0] 520 ldr r0, =0x1e7891a4 521 ldr r1, =0x2000 522 str r1, [r0] 523 ldr r0, =0x1e7891a8 524 ldr r1, =0x3ff 525 str r1, [r0] 526 ldr r0, =0x1e7891ac 527 str r2, [r0] 528 ldr r0, =0x1e789240 529 mov r1, #0xff 530 str r1, [r0] 531 ldr r0, =0x1e789244 532 str r1, [r0] 533 ldr r0, =0x1e789248 534 mov r1, #0x80 535 str r1, [r0] 536 ldr r0, =0x1e789250 537 str r2, [r0] 538 ldr r0, =0x1e789254 539 str r2, [r0] 540 /***** Clear LPC status : End *****/ 541 542 ldr r0, =0x1e62009c @ clear software strap flag for doing again after reset 543 ldr r1, =0xAEEDFC20 544 str r1, [r0] 545 ldr r0, =0x1e785004 546 ldr r1, =0x00000001 547 str r1, [r0] 548 ldr r0, =0x1e785008 549 ldr r1, =0x00004755 550 str r1, [r0] 551 ldr r0, =0x1e78501c @ enable full mask of SOC reset 552 ldr r1, =0x03FFFFFF @ added 2016.09.06 553 str r1, [r0] 554 ldr r0, =0x1e78500c @ enable SOC reset 555 ldr r1, =0x00000013 556 str r1, [r0] 557#endif 558wait_first_reset: 559 b wait_first_reset 560 561 /******************************************** 562 Initial Reset Procedure : End 563 *******************************************/ 564 565bypass_first_reset: 566 /* Enable Timer separate clear mode */ 567 ldr r0, =0x1e782038 568 mov r1, #0xAE 569 str r1, [r0] 570 571/* Test - DRAM initial time */ 572 ldr r0, =0x1e78203c 573 ldr r1, =0x0000F000 574 str r1, [r0] 575 576 ldr r0, =0x1e782044 577 ldr r1, =0xFFFFFFFF 578 str r1, [r0] 579 580 ldr r0, =0x1e782030 581 mov r2, #3 582 mov r1, r2, lsl #12 583 str r1, [r0] 584/* Test - DRAM initial time */ 585 586 /*Set Scratch register Bit 7 before initialize*/ 587 ldr r0, =0x1e6e2000 588 ldr r1, =0x1688a8a8 589 str r1, [r0] 590 591 ldr r0, =0x1e6e2040 592 ldr r1, [r0] 593 orr r1, r1, #0x80 594 str r1, [r0] 595 596 /* Change LPC reset source to PERST# when eSPI mode enabled */ 597 ldr r0, =0x1e6e2070 598 ldr r1, [r0] 599 ldr r0, =0x1e6e207c 600 ldr r2, =0x02000000 601 ldr r3, =0x00004000 602 tst r1, r2 603 strne r3, [r0] 604 605 /* Configure USB ports to the correct pin state */ 606 ldr r0, =0x1e6e200c @ enable portA clock 607 ldr r2, =0x00004000 608 ldr r1, [r0] 609 orr r1, r1, r2 610 str r1, [r0] 611 ldr r0, =0x1e6e2090 @ set portA as host mode 612 ldr r1, =0x2000A000 613 str r1, [r0] 614 ldr r0, =0x1e6e2094 @ set portB as host mode 615 ldr r1, =0x00004000 616 str r1, [r0] 617 ldr r0, =0x1e6e2070 618 ldr r2, =0x00800000 619 ldr r1, [r0] 620 tst r1, r2 621 beq bypass_USB_init 622 ldr r0, =0x1e6e207c 623 str r2, [r0] 624 625 /* Delay about 1ms */ 626 clear_delay_timer 627 ldr r2, =0x000003E8 @ Set Timer3 Reload = 1 ms 628 init_delay_timer 629wait_usb_init: 630 check_delay_timer 631 bne wait_usb_init 632 clear_delay_timer 633 /* end delay 1ms */ 634 635 ldr r0, =0x1e6e2070 636 ldr r1, =0x00800000 637 str r1, [r0] 638 639bypass_USB_init: 640 /* Enable AXI_P */ 641 ldr r0, =0x00000016 642 mrc p15, 0, r1, c15, c2, 4 643 mcr p15, 0, r0, c15, c2, 4 644 645/****************************************************************************** 646 Disable WDT2 for 2nd boot function 647 ******************************************************************************/ 648/* 649#ifndef CONFIG_FIRMWARE_2ND_BOOT 650 ldr r0, =0x1e78502c 651 mov r1, #0 652 str r1, [r0] 653#endif 654*/ 655/****************************************************************************** 656 Disable WDT3 for SPI Address mode (3 or 4 bytes) detection function 657 ******************************************************************************/ 658 ldr r0, =0x1e78504c 659 mov r1, #0 660 str r1, [r0] 661 662 ldr r0, =0x1e6e0000 663 ldr r1, =0xFC600309 664 str r1, [r0] 665 666#ifdef CONFIG_SPL_BUILD 667 /* SPL: leave the rest to U-Boot proper */ 668 mov pc, lr 669#else 670 /* skip SDRAM initialization (will be done in C function) */ 671 b platform_exit 672#endif 673 674 /* Check Scratch Register Bit 6 */ 675 ldr r0, =0x1e6e2040 676 ldr r1, [r0] 677 bic r1, r1, #0xFFFFFFBF 678 mov r2, r1, lsr #6 679 cmp r2, #0x01 680 beq platform_exit 681 682 /* Disable VGA display */ 683 ldr r0, =0x1e6e202c 684 ldr r1, [r0] 685 orr r1, r1, #0x40 686 str r1, [r0] 687 688 ldr r0, =0x1e6e2070 @ Load strap register 689 ldr r3, [r0] 690 691 /* Set M-PLL */ 692#if defined (CONFIG_DRAM_1333) 693 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330) 694#else 695 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396) 696#if defined (CONFIG_DDR4_SUPPORT_HYNIX) 697 mov r1, r3, lsr #24 @ Check DDR4 698 tst r1, #0x01 699 beq bypass_mpll_hynix_mode_1 700#if defined (CONFIG_DDR4_HYNIX_SET_1536) 701 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384) 702#elif defined (CONFIG_DDR4_HYNIX_SET_1488) 703 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372) 704#else 705 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360) 706#endif 707bypass_mpll_hynix_mode_1: 708#endif 709#endif 710 711 mov r1, r3, lsr #23 @ Check CLKIN = 25MHz 712 tst r1, #0x01 713 beq set_MPLL 714#if defined (CONFIG_DRAM_1333) 715 ldr r2, =0xC4806680 @ load PLL parameter for 25Mhz CLKIN (331) 716#else 717 ldr r2, =0x930023E0 @ load PLL parameter for 25Mhz CLKIN (400) 718#if defined (CONFIG_DDR4_SUPPORT_HYNIX) 719 mov r1, r3, lsr #24 @ Check DDR4 720 tst r1, #0x01 721 beq bypass_mpll_hynix_mode_2 722#if defined (CONFIG_DDR4_HYNIX_SET_1536) 723 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (387.5) 724#elif defined (CONFIG_DDR4_HYNIX_SET_1488) 725 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (375) 726#else 727 ldr r2, =0x93002380 @ load PLL parameter for 24Mhz CLKIN (362.5) 728#endif 729bypass_mpll_hynix_mode_2: 730#endif 731#endif 732 ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz) 733 ldr r1, =0x00011320 734 str r1, [r0] 735 736set_MPLL: 737 ldr r0, =0x1e6e2020 @ M-PLL (DDR SDRAM) Frequency 738 str r2, [r0] 739 740 clear_delay_timer 741 742 /* Delay about 3ms */ 743 ldr r2, =0x00000BB8 @ Set Timer3 Reload = 3 ms 744 init_delay_timer 745wait_mpll_init: 746 check_delay_timer 747 bne wait_mpll_init 748 clear_delay_timer 749 /* end delay 3ms */ 750 751 /* Reset MMC */ 752reset_mmc: 753 ldr r0, =0x1e78505c 754 ldr r1, =0x00000004 755 str r1, [r0] 756 ldr r0, =0x1e785044 757 ldr r1, =0x00000001 758 str r1, [r0] 759 ldr r0, =0x1e785048 760 ldr r1, =0x00004755 761 str r1, [r0] 762 ldr r0, =0x1e78504c 763 ldr r1, =0x00000013 764 str r1, [r0] 765wait_mmc_reset: 766 ldr r1, [r0] 767 tst r1, #0x02 768 bne wait_mmc_reset 769 770 ldr r0, =0x1e78505c 771 ldr r1, =0x023FFFF3 772 str r1, [r0] 773 ldr r0, =0x1e785044 774 ldr r1, =0x000F4240 775 str r1, [r0] 776 ldr r0, =0x1e785048 777 ldr r1, =0x00004755 778 str r1, [r0] 779 ldr r0, =0x1e785054 780 ldr r1, =0x00000077 781 str r1, [r0] 782 783 ldr r0, =0x1e6e0000 784 ldr r1, =0xFC600309 785wait_mmc_reset_done: 786 str r1, [r0] 787 ldr r2, [r0] 788 cmp r2, #0x1 789 bne wait_mmc_reset_done 790 791 ldr r0, =0x1e6e0034 @ disable MMC request 792 ldr r1, =0x00020000 793 str r1, [r0] 794 795 /* Delay about 10ms */ 796 ldr r2, =0x00002710 @ Set Timer3 Reload = 10 ms 797 init_delay_timer 798wait_ddr_reset: 799 check_delay_timer 800 bne wait_ddr_reset 801 clear_delay_timer 802 /* end delay 10ms */ 803 804/* Debug - UART console message */ 805#ifdef CONFIG_DRAM_UART_TO_UART1 806 ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29 807 ldr r1, =0x10000004 808 str r1, [r0] 809 810 ldr r0, =0x1e6e2084 811 ldr r1, [r0] 812 mov r2, #0xC0 @ Enable pinmux of TXD1/RXD1 813 orr r1, r1, r2, lsl #16 814 str r1, [r0] 815#endif 816 817 ldr r0, =0x1e78400c 818 mov r1, #0x83 819 str r1, [r0] 820 821 ldr r0, =0x1e6e202c 822 ldr r2, [r0] 823 mov r2, r2, lsr #12 824 tst r2, #0x01 825 ldr r0, =0x1e784000 826 moveq r1, #0x0D @ Baudrate 115200 827 movne r1, #0x01 @ Baudrate 115200, div13 828#ifdef CONFIG_DRAM_UART_38400 829 moveq r1, #0x27 @ Baudrate 38400 830 movne r1, #0x03 @ Baudrate 38400 , div13 831#endif 832 str r1, [r0] 833 834 ldr r0, =0x1e784004 835 mov r1, #0x00 836 str r1, [r0] 837 838 ldr r0, =0x1e78400c 839 mov r1, #0x03 840 str r1, [r0] 841 842 ldr r0, =0x1e784008 843 mov r1, #0x07 844 str r1, [r0] 845 846 ldr r0, =0x1e784000 847 mov r1, #0x0D @ '\r' 848 str r1, [r0] 849 mov r1, #0x0A @ '\n' 850 str r1, [r0] 851 mov r1, #0x44 @ 'D' 852 str r1, [r0] 853 mov r1, #0x52 @ 'R' 854 str r1, [r0] 855 mov r1, #0x41 @ 'A' 856 str r1, [r0] 857 mov r1, #0x4D @ 'M' 858 str r1, [r0] 859 mov r1, #0x20 @ ' ' 860 str r1, [r0] 861 mov r1, #0x49 @ 'I' 862 str r1, [r0] 863 mov r1, #0x6E @ 'n' 864 str r1, [r0] 865 mov r1, #0x69 @ 'i' 866 str r1, [r0] 867 mov r1, #0x74 @ 't' 868 str r1, [r0] 869 mov r1, #0x2D @ '-' 870 str r1, [r0] 871 mov r1, #0x56 @ 'V' 872 str r1, [r0] 873 mov r1, #ASTMMC_INIT_VER 874 mov r1, r1, lsr #4 875 print_hex_char 876 mov r1, #ASTMMC_INIT_VER 877 print_hex_char 878 mov r1, #0x2D @ '-' 879 str r1, [r0] 880 ldr r0, =0x1e784014 881wait_print: 882 ldr r1, [r0] 883 tst r1, #0x40 884 beq wait_print 885 ldr r0, =0x1e784000 886 mov r1, #0x44 @ 'D' 887 str r1, [r0] 888 mov r1, #0x44 @ 'D' 889 str r1, [r0] 890 mov r1, #0x52 @ 'R' 891 str r1, [r0] 892/* Debug - UART console message */ 893 894/****************************************************************************** 895 Init DRAM common registers 896 ******************************************************************************/ 897 ldr r0, =0x1e6e0034 @ disable SDRAM reset 898 ldr r1, =0x00020080 899 str r1, [r0] 900 901 ldr r0, =0x1e6e0008 902 ldr r1, =0x2003000F /* VGA */ 903 str r1, [r0] 904 905 ldr r0, =0x1e6e0038 @ disable all DRAM requests except CPU during PHY init 906 ldr r1, =0xFFFFEBFF 907 str r1, [r0] 908 909 ldr r0, =0x1e6e0040 910 ldr r1, =0x88448844 911 str r1, [r0] 912 913 ldr r0, =0x1e6e0044 914 ldr r1, =0x24422288 915 str r1, [r0] 916 917 ldr r0, =0x1e6e0048 918 ldr r1, =0x22222222 919 str r1, [r0] 920 921 ldr r0, =0x1e6e004c 922 ldr r1, =0x22222222 923 str r1, [r0] 924 925 ldr r0, =0x1e6e0050 926 ldr r1, =0x80000000 927 str r1, [r0] 928 929 ldr r1, =0x00000000 930 ldr r0, =0x1e6e0208 @ PHY Setting 931 str r1, [r0] 932 ldr r0, =0x1e6e0218 933 str r1, [r0] 934 ldr r0, =0x1e6e0220 935 str r1, [r0] 936 ldr r0, =0x1e6e0228 937 str r1, [r0] 938 ldr r0, =0x1e6e0230 939 str r1, [r0] 940 ldr r0, =0x1e6e02a8 941 str r1, [r0] 942 ldr r0, =0x1e6e02b0 943 str r1, [r0] 944 945 ldr r0, =0x1e6e0240 946 ldr r1, =0x86000000 947 str r1, [r0] 948 949 ldr r0, =0x1e6e0244 950 ldr r1, =0x00008600 951 str r1, [r0] 952 953 ldr r0, =0x1e6e0248 954 ldr r1, =0x80000000 955 str r1, [r0] 956 957 ldr r0, =0x1e6e024c 958 ldr r1, =0x80808080 959 str r1, [r0] 960 961 /* Check DRAM Type by H/W Trapping */ 962 ldr r0, =0x1e6e2070 963 ldr r1, [r0] 964 ldr r2, =0x01000000 @ bit[24]=1 => DDR4 965 tst r1, r2 966 bne ddr4_init 967 b ddr3_init 968.LTORG 969 970/****************************************************************************** 971 DDR3 Init 972 ******************************************************************************/ 973ddr3_init: 974/* Debug - UART console message */ 975 ldr r0, =0x1e784000 976 mov r1, #0x33 @ '3' 977 str r1, [r0] 978 mov r1, #0x0D @ '\r' 979 str r1, [r0] 980 mov r1, #0x0A @ '\n' 981 str r1, [r0] 982/* Debug - UART console message */ 983 984#if defined (CONFIG_DRAM_1333) 985 adrl r5, TIME_TABLE_DDR3_1333 @ Init DRAM parameter table 986#else 987 adrl r5, TIME_TABLE_DDR3_1600 988#endif 989 990 ldr r0, =0x1e6e0004 991#ifdef CONFIG_DDR3_8GSTACK 992 ldr r1, =0x00000323 @ Init to 8GB stack 993#else 994 ldr r1, =0x00000303 @ Init to 8GB 995#endif 996 str r1, [r0] 997 998 ldr r0, =0x1e6e0010 999 ldr r1, [r5, #ASTMMC_REGIDX_010] 1000 str r1, [r0] 1001 1002 ldr r0, =0x1e6e0014 1003 ldr r1, [r5, #ASTMMC_REGIDX_014] 1004 str r1, [r0] 1005 1006 ldr r0, =0x1e6e0018 1007 ldr r1, [r5, #ASTMMC_REGIDX_018] 1008 str r1, [r0] 1009 1010 /* DRAM Mode Register Setting */ 1011 ldr r0, =0x1e6e0020 @ MRS_4/6 1012 ldr r1, [r5, #ASTMMC_REGIDX_020] 1013 str r1, [r0] 1014 1015 ldr r0, =0x1e6e0024 @ MRS_5 1016 ldr r1, [r5, #ASTMMC_REGIDX_024] 1017 str r1, [r0] 1018 1019 ldr r0, =0x1e6e002c @ MRS_0/2 1020 ldr r1, [r5, #ASTMMC_REGIDX_02C] 1021 mov r2, #0x1 1022 orr r1, r1, r2, lsl #8 1023 str r1, [r0] 1024 1025 ldr r0, =0x1e6e0030 @ MRS_1/3 1026 ldr r1, [r5, #ASTMMC_REGIDX_030] 1027 str r1, [r0] 1028 1029 /* Start DDR PHY Setting */ 1030 ldr r0, =0x1e6e0200 1031 ldr r1, =0x02492AAE 1032 str r1, [r0] 1033 1034 ldr r0, =0x1e6e0204 1035#ifdef CONFIG_DDR3_8GSTACK 1036 ldr r1, =0x10001001 1037#else 1038 ldr r1, =0x00001001 1039#endif 1040 str r1, [r0] 1041 1042 ldr r0, =0x1e6e020c 1043 ldr r1, =0x55E00B0B 1044 str r1, [r0] 1045 1046 ldr r0, =0x1e6e0210 1047 ldr r1, =0x20000000 1048 str r1, [r0] 1049 1050 ldr r0, =0x1e6e0214 1051 ldr r1, [r5, #ASTMMC_REGIDX_214] 1052 str r1, [r0] 1053 1054 ldr r0, =0x1e6e02e0 1055 ldr r1, [r5, #ASTMMC_REGIDX_2E0] 1056 str r1, [r0] 1057 1058 ldr r0, =0x1e6e02e4 1059 ldr r1, [r5, #ASTMMC_REGIDX_2E4] 1060 str r1, [r0] 1061 1062 ldr r0, =0x1e6e02e8 1063 ldr r1, [r5, #ASTMMC_REGIDX_2E8] 1064 str r1, [r0] 1065 1066 ldr r0, =0x1e6e02ec 1067 ldr r1, [r5, #ASTMMC_REGIDX_2EC] 1068 str r1, [r0] 1069 1070 ldr r0, =0x1e6e02f0 1071 ldr r1, [r5, #ASTMMC_REGIDX_2F0] 1072 str r1, [r0] 1073 1074 ldr r0, =0x1e6e02f4 1075 ldr r1, [r5, #ASTMMC_REGIDX_2F4] 1076 str r1, [r0] 1077 1078 ldr r0, =0x1e6e02f8 1079 ldr r1, [r5, #ASTMMC_REGIDX_2F8] 1080 str r1, [r0] 1081 1082 ldr r0, =0x1e6e0290 1083 ldr r1, =0x00100008 1084 str r1, [r0] 1085 1086 ldr r0, =0x1e6e02c0 1087 ldr r1, =0x00000006 1088 str r1, [r0] 1089 1090 /* Controller Setting */ 1091 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1092 ldr r1, =0x00000005 1093 str r1, [r0] 1094 1095 ldr r0, =0x1e6e0034 1096 ldr r1, =0x00020091 1097 str r1, [r0] 1098 1099/* Debug - UART console message */ 1100 ldr r0, =0x1e784000 1101 mov r1, #0x30 @ '0' 1102 str r1, [r0] 1103/* Debug - UART console message */ 1104 1105 ldr r0, =0x1e6e0120 1106 mov r1, #0x00 1107 str r1, [r0] 1108 b ddr_phy_init_process 1109 1110ddr3_phyinit_done: 1111 1112 /******************************************** 1113 Check Read training margin 1114 ********************************************/ 1115 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window 1116 ldr r1, [r0] 1117 ldr r2, =0x150 1118 bic r0, r1, #0xFF000000 1119 bic r0, r0, #0x00FF0000 1120 cmp r0, r2 1121 blt ddr_test_fail 1122 mov r0, r1, lsr #16 1123 cmp r0, r2 1124 blt ddr_test_fail 1125 1126 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window 1127 ldr r1, [r0] 1128 ldr r2, =0x90 1129 bic r0, r1, #0x0000FF00 1130 cmp r0, r2 1131 blt ddr_test_fail 1132 mov r0, r1, lsr #8 1133 cmp r0, r2 1134 blt ddr_test_fail 1135 /*******************************************/ 1136 1137/* Debug - UART console message */ 1138 ldr r0, =0x1e784000 1139 mov r1, #0x31 @ '1' 1140 str r1, [r0] 1141/* Debug - UART console message */ 1142 1143 ldr r0, =0x1e6e000c 1144 ldr r1, =0x00000040 1145 str r1, [r0] 1146 1147#ifdef CONFIG_DDR3_8GSTACK 1148 ldr r0, =0x1e6e0028 1149 ldr r1, =0x00000025 1150 str r1, [r0] 1151 1152 ldr r0, =0x1e6e0028 1153 ldr r1, =0x00000027 1154 str r1, [r0] 1155 1156 ldr r0, =0x1e6e0028 1157 ldr r1, =0x00000023 1158 str r1, [r0] 1159 1160 ldr r0, =0x1e6e0028 1161 ldr r1, =0x00000021 1162 str r1, [r0] 1163#endif 1164 1165 ldr r0, =0x1e6e0028 1166 ldr r1, =0x00000005 1167 str r1, [r0] 1168 1169 ldr r0, =0x1e6e0028 1170 ldr r1, =0x00000007 1171 str r1, [r0] 1172 1173 ldr r0, =0x1e6e0028 1174 ldr r1, =0x00000003 1175 str r1, [r0] 1176 1177 ldr r0, =0x1e6e0028 1178 ldr r1, =0x00000011 1179 str r1, [r0] 1180 1181 ldr r0, =0x1e6e000c 1182 ldr r1, =0x00005C41 1183 str r1, [r0] 1184 1185 ldr r0, =0x1e6e0034 1186 ldr r2, =0x70000000 1187ddr3_check_dllrdy: 1188 ldr r1, [r0] 1189 tst r1, r2 1190 bne ddr3_check_dllrdy 1191 1192 ldr r0, =0x1e6e000c 1193#ifdef CONFIG_DRAM_EXT_TEMP 1194 ldr r1, =0x42AA2F81 1195#else 1196 ldr r1, =0x42AA5C81 1197#endif 1198 str r1, [r0] 1199 1200 ldr r0, =0x1e6e0034 1201 ldr r1, =0x0001AF93 1202 str r1, [r0] 1203 1204 ldr r0, =0x1e6e0120 @ VGA Compatible Mode 1205 ldr r1, [r5, #ASTMMC_REGIDX_PLL] 1206 str r1, [r0] 1207 1208 b Calibration_End 1209.LTORG 1210/****************************************************************************** 1211 End DDR3 Init 1212 ******************************************************************************/ 1213/****************************************************************************** 1214 DDR4 Init 1215 ******************************************************************************/ 1216ddr4_init: 1217/* Debug - UART console message */ 1218 ldr r0, =0x1e784000 1219 mov r1, #0x34 @ '4' 1220 str r1, [r0] 1221 mov r1, #0x0D @ '\r' 1222 str r1, [r0] 1223 mov r1, #0x0A @ '\n' 1224 str r1, [r0] 1225/* Debug - UART console message */ 1226 1227#if defined (CONFIG_DRAM_1333) 1228 adrl r5, TIME_TABLE_DDR4_1333 @ Init DRAM parameter table 1229#else 1230 adrl r5, TIME_TABLE_DDR4_1600 1231#endif 1232 1233 ldr r0, =0x1e6e0004 1234#ifdef CONFIG_DDR4_4GX8 1235 ldr r1, =0x00002313 @ Init to 8GB 1236#else 1237 ldr r1, =0x00000313 @ Init to 8GB 1238#endif 1239 str r1, [r0] 1240 1241 ldr r0, =0x1e6e0010 1242 ldr r1, [r5, #ASTMMC_REGIDX_010] 1243 str r1, [r0] 1244 1245 ldr r0, =0x1e6e0014 1246 ldr r1, [r5, #ASTMMC_REGIDX_014] 1247 str r1, [r0] 1248 1249 ldr r0, =0x1e6e0018 1250 ldr r1, [r5, #ASTMMC_REGIDX_018] 1251 str r1, [r0] 1252 1253 /* DRAM Mode Register Setting */ 1254 ldr r0, =0x1e6e0020 @ MRS_4/6 1255 ldr r1, [r5, #ASTMMC_REGIDX_020] 1256 str r1, [r0] 1257 1258 ldr r0, =0x1e6e0024 @ MRS_5 1259 ldr r1, [r5, #ASTMMC_REGIDX_024] 1260 str r1, [r0] 1261 1262 ldr r0, =0x1e6e002c @ MRS_0/2 1263 ldr r1, [r5, #ASTMMC_REGIDX_02C] 1264 mov r2, #0x1 1265 orr r1, r1, r2, lsl #8 1266 str r1, [r0] 1267 1268 ldr r0, =0x1e6e0030 @ MRS_1/3 1269 ldr r1, [r5, #ASTMMC_REGIDX_030] 1270 str r1, [r0] 1271 1272 /* Start DDR PHY Setting */ 1273 ldr r0, =0x1e6e0200 1274 ldr r1, =0x42492AAE 1275 str r1, [r0] 1276 1277 ldr r0, =0x1e6e0204 1278 ldr r1, =0x09002800 1279 str r1, [r0] 1280 1281 ldr r0, =0x1e6e020c 1282 ldr r1, =0x55E00B0B 1283 str r1, [r0] 1284 1285 ldr r0, =0x1e6e0210 1286 ldr r1, =0x20000000 1287 str r1, [r0] 1288 1289 ldr r0, =0x1e6e0214 1290 ldr r1, [r5, #ASTMMC_REGIDX_214] 1291 str r1, [r0] 1292 1293 ldr r0, =0x1e6e02e0 1294 ldr r1, [r5, #ASTMMC_REGIDX_2E0] 1295 str r1, [r0] 1296 1297 ldr r0, =0x1e6e02e4 1298 ldr r1, [r5, #ASTMMC_REGIDX_2E4] 1299 str r1, [r0] 1300 1301 ldr r0, =0x1e6e02e8 1302 ldr r1, [r5, #ASTMMC_REGIDX_2E8] 1303 str r1, [r0] 1304 1305 ldr r0, =0x1e6e02ec 1306 ldr r1, [r5, #ASTMMC_REGIDX_2EC] 1307 str r1, [r0] 1308 1309 ldr r0, =0x1e6e02f0 1310 ldr r1, [r5, #ASTMMC_REGIDX_2F0] 1311 str r1, [r0] 1312 1313 ldr r0, =0x1e6e02f4 1314 ldr r1, [r5, #ASTMMC_REGIDX_2F4] 1315 str r1, [r0] 1316 1317 ldr r0, =0x1e6e02f8 1318 ldr r1, [r5, #ASTMMC_REGIDX_2F8] 1319 str r1, [r0] 1320 1321 ldr r0, =0x1e6e0290 1322 ldr r1, =0x00100008 1323 str r1, [r0] 1324 1325 ldr r0, =0x1e6e02c4 1326 ldr r1, =0x3C183C3C 1327 str r1, [r0] 1328 1329 ldr r0, =0x1e6e02c8 1330 ldr r1, =0x00631E0E 1331 str r1, [r0] 1332 1333 ldr r0, =0x1e6e0034 1334 ldr r1, =0x0001A991 1335 str r1, [r0] 1336 1337/* Debug - UART console message */ 1338 ldr r0, =0x1e784000 1339 mov r1, #0x30 @ '0' 1340 str r1, [r0] 1341/* Debug - UART console message */ 1342 1343 /******************************************** 1344 Set Ron value to manual mode 1345 Target to fix DDR CK Vix issue 1346 Set Ron_pu = 0, Ron_pd = trained value 1347 *******************************************/ 1348#ifdef ASTMMC_DDR4_MANUAL_RPU 1349 ldr r0, =0x1e6e02c0 1350 ldr r1, =0x00001806 1351 str r1, [r0] 1352 ldr r0, =0x1e6e02cc 1353 ldr r1, =0x00005050 1354 str r1, [r0] 1355 ldr r0, =0x1e6e0120 1356 mov r1, #0x04 1357 str r1, [r0] 1358 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1359 mov r1, #0x05 1360 str r1, [r0] 1361 b ddr_phy_init_process 1362 1363ddr4_ron_phyinit_done: 1364 1365 ldr r0, =0x1e6e0300 @ read calibrated Ron_pd 1366 ldr r3, [r0] 1367 bic r3, r3, #0xFFFFFF0F 1368 ldr r0, =0x1e6e0240 1369 ldr r1, [r0] 1370 bic r1, r1, #0xFF000000 1371 mov r2, #ASTMMC_DDR4_MANUAL_RPU 1372 orr r1, r1, r2, lsl #24 1373#ifdef ASTMMC_DDR4_MANUAL_RPD 1374 mov r2, #ASTMMC_DDR4_MANUAL_RPD 1375 orr r1, r1, r2, lsl #28 1376#else 1377 orr r1, r1, r3, lsl #24 1378#endif 1379 orr r1, r1, #0x02 1380 str r1, [r0] 1381 1382 ldr r0, =0x1e6e0060 @ Reset PHY 1383 mov r1, #0x00 1384 str r1, [r0] 1385#endif 1386 /******************************************** 1387 PHY Vref Scan 1388 r6 : recorded vref value 1389 r7 : max read eye pass window 1390 r8 : passcnt 1391 r9 : CBRtest result 1392 r10: loopcnt 1393 r11: free 1394 ********************************************/ 1395 ldr r0, =0x1e720000 @ retry count 1396 mov r1, #0x5 1397 str r1, [r0] 1398ddr4_vref_phy_cal_start: 1399 mov r7, #0x0 1400 mov r8, #0x0 1401 mov r10, #0x3F 1402 1403 ldr r0, =0x1e720000 1404 ldr r1, [r0] 1405 subs r1, r1, #0x01 1406 beq ddr_test_fail 1407 str r1, [r0] 1408 1409 ldr r0, =0x1e6e0120 1410 ldr r1, =0x00000001 1411 str r1, [r0] 1412 1413/* Debug - UART console message */ 1414 ldr r0, =0x1e784000 1415 mov r1, #0x61 @ 'a' 1416 str r1, [r0] 1417/* Debug - UART console message */ 1418 1419 ldr r0, =0x1e6e02c0 1420 ldr r1, =0x00001C06 1421 str r1, [r0] 1422 1423ddr4_vref_phy_loop: 1424 ldr r0, =0x1e6e0060 1425 ldr r1, =0x00000000 1426 str r1, [r0] 1427 1428 add r10, r10, #0x01 1429 cmp r10, #0x80 1430 beq ddr4_vref_phy_test_fail @ no valid margin and retry 1431 1432 ldr r0, =0x1e6e02cc 1433 orr r1, r10, r10, lsl #8 1434 str r1, [r0] 1435 1436 ldr r0, =0x1e6e0060 1437 ldr r1, =0x00000005 1438 str r1, [r0] 1439 b ddr_phy_init_process 1440 1441ddr4_vref_phy_phyinit_done: 1442 1443 b cbr_test_start 1444 1445ddr4_vref_phy_cbrtest_done: 1446 ldr r0, =0x1e6e03d0 @ read eye pass window 1447 ldr r1, [r0] 1448 ldr r0, =0x1e720000 1449 add r0, r0, r10, lsl #2 1450 str r1, [r0] 1451 cmp r9, #0x01 1452 bne ddr4_vref_phy_test_fail 1453 add r8, r8, #0x01 1454 ldr r0, =0x1e6e03d0 @ read eye pass window 1455 ldr r1, [r0] 1456 mov r2, r1, lsr #8 @ r2 = DQH 1457 and r1, r1, #0xFF @ r1 = DQL 1458 cmp r1, r2 1459 movgt r1, r2 @ r1 = smaller one 1460 cmp r1, r7 1461 movgt r6, r10 1462 movgt r7, r1 1463 b ddr4_vref_phy_loop 1464 1465ddr4_vref_phy_test_fail: 1466 cmp r8, #0x0 1467 bne ddr4_vref_phy_loop_end 1468 cmp r10, #0x80 1469 beq ddr4_vref_phy_cal_start 1470 b ddr4_vref_phy_loop 1471 1472ddr4_vref_phy_loop_end: 1473 cmp r8, #16 @ check phyvref margin >= 16 1474 blt ddr_test_fail 1475 ldr r0, =0x1e6e02cc 1476 orr r1, r6, r6, lsl #8 1477 str r1, [r0] 1478 ldr r0, =0x1e720010 1479 orr r1, r6, r7, lsl #8 1480 orr r1, r1, r8, lsl #16 1481 str r1, [r0] 1482 1483 /******************************************** 1484 DDR Vref Scan 1485 r6 : min 1486 r7 : max 1487 r8 : passcnt 1488 r9 : CBRtest result 1489 r10: loopcnt 1490 r11: free 1491 ********************************************/ 1492 ldr r0, =0x1e720000 @ retry count 1493 mov r1, #0x5 1494 str r1, [r0] 1495ddr4_vref_ddr_cal_start: 1496 mov r6, #0xFF 1497 mov r7, #0x0 1498 mov r8, #0x0 1499 mov r10, #0x0 1500 1501 ldr r0, =0x1e720000 1502 ldr r1, [r0] 1503 subs r1, r1, #0x01 1504 beq ddr_test_fail 1505 str r1, [r0] 1506 1507 ldr r0, =0x1e6e0120 1508 ldr r1, =0x00000002 1509 str r1, [r0] 1510 1511/* Debug - UART console message */ 1512 ldr r0, =0x1e784000 1513 mov r1, #0x62 @ 'b' 1514 str r1, [r0] 1515/* Debug - UART console message */ 1516 1517ddr4_vref_ddr_loop: 1518 ldr r0, =0x1e6e0060 1519 ldr r1, =0x00000000 1520 str r1, [r0] 1521 1522 add r10, r10, #0x01 1523 cmp r10, #0x40 1524 beq ddr4_vref_ddr_test_fail @ no valid margin and retry 1525 1526 ldr r0, =0x1e6e02c0 1527 mov r1, #0x06 1528 orr r1, r1, r10, lsl #8 1529 str r1, [r0] 1530 1531 ldr r0, =0x1e6e0060 1532 ldr r1, =0x00000005 1533 str r1, [r0] 1534 b ddr_phy_init_process 1535 1536ddr4_vref_ddr_phyinit_done: 1537 1538 b cbr_test_start 1539 1540ddr4_vref_ddr_cbrtest_done: 1541 cmp r9, #0x01 1542 bne ddr4_vref_ddr_test_fail 1543 add r8, r8, #0x01 1544 cmp r6, r10 1545 movgt r6, r10 1546 cmp r7, r10 1547 movlt r7, r10 1548 b ddr4_vref_ddr_loop 1549 1550ddr4_vref_ddr_test_fail: 1551 cmp r8, #0x0 1552 bne ddr4_vref_ddr_loop_end 1553 cmp r10, #0x40 1554 beq ddr4_vref_ddr_cal_start 1555 b ddr4_vref_ddr_loop 1556 1557ddr4_vref_ddr_loop_end: 1558 ldr r0, =0x1e6e0060 1559 ldr r1, =0x00000000 1560 str r1, [r0] 1561 1562 cmp r8, #16 @ check ddrvref margin >= 16 1563 blt ddr_test_fail 1564 ldr r0, =0x1e6e02c0 1565 add r1, r6, r7 1566 add r1, r1, #0x01 1567 mov r2, r1, lsr #1 1568 mov r1, r2, lsl #8 1569 orr r1, r1, #0x06 1570 str r1, [r0] 1571 ldr r0, =0x1e720014 1572 orr r1, r6, r7, lsl #8 1573 orr r1, r1, r8, lsl #16 1574 str r1, [r0] 1575 1576/* Debug - UART console message */ 1577 ldr r0, =0x1e784000 1578 mov r1, #0x63 @ 'c' 1579 str r1, [r0] 1580/* Debug - UART console message */ 1581 1582 ldr r0, =0x1e6e0120 1583 ldr r1, =0x00000003 1584 str r1, [r0] 1585 1586 ldr r0, =0x1e6e0060 @ Fire DDRPHY Init 1587 ldr r1, =0x00000005 1588 str r1, [r0] 1589 b ddr_phy_init_process 1590 1591ddr4_phyinit_done: 1592 1593 /******************************************** 1594 Check Read training margin 1595 ********************************************/ 1596 ldr r0, =0x1e6e03a0 @ check Gate Training Pass Window 1597 ldr r1, [r0] 1598 ldr r2, =0x150 1599 bic r0, r1, #0xFF000000 1600 bic r0, r0, #0x00FF0000 1601 cmp r0, r2 1602 blt ddr_test_fail 1603 mov r0, r1, lsr #16 1604 cmp r0, r2 1605 blt ddr_test_fail 1606 1607 ldr r0, =0x1e6e03d0 @ check Read Data Eye Training Pass Window 1608 ldr r1, [r0] 1609 ldr r2, =0x90 1610 bic r0, r1, #0x0000FF00 1611 cmp r0, r2 1612 blt ddr_test_fail 1613 mov r0, r1, lsr #8 1614 cmp r0, r2 1615 blt ddr_test_fail 1616 /*******************************************/ 1617 1618 /*******************************************/ 1619/* Debug - UART console message */ 1620 ldr r0, =0x1e784000 1621 mov r1, #0x31 @ '1' 1622 str r1, [r0] 1623/* Debug - UART console message */ 1624 1625 ldr r0, =0x1e6e000c 1626#ifdef CONFIG_DRAM_EXT_TEMP 1627 ldr r1, =0x42AA2F81 1628#else 1629 ldr r1, =0x42AA5C81 1630#endif 1631 str r1, [r0] 1632 1633 ldr r0, =0x1e6e0034 1634 ldr r1, =0x0001AF93 1635 str r1, [r0] 1636 1637 ldr r0, =0x1e6e0120 @ VGA Compatible Mode 1638 ldr r1, [r5, #ASTMMC_REGIDX_PLL] 1639 str r1, [r0] 1640 1641 b Calibration_End 1642 1643.LTORG 1644/****************************************************************************** 1645 End DDR4 Init 1646 ******************************************************************************/ 1647/****************************************************************************** 1648 Global Process 1649 ******************************************************************************/ 1650 /******************************************** 1651 DDRPHY Init Process 1652 ********************************************/ 1653ddr_phy_init_process: 1654 clear_delay_timer 1655 /* Wait DDR PHY init done - timeout 300 ms */ 1656 ldr r2, =0x000493E0 @ Set Timer3 Reload = 300 ms 1657 init_delay_timer 1658 ldr r3, =0x1e6e0060 1659ddr_phy_init: 1660 check_delay_timer 1661 beq ddr_phy_init_timeout 1662 ldr r1, [r3] 1663 tst r1, #0x01 1664 bne ddr_phy_init 1665 1666 /* Check DDR PHY init status */ 1667 ldr r0, =0x1e6e0300 1668 ldr r2, =0x000A0000 1669 ldr r1, [r0] 1670 tst r1, r2 1671 beq ddr_phy_init_success 1672 1673ddr_phy_init_timeout: 1674 ldr r0, =0x1e6e0060 @ Reset PHY 1675 mov r1, #0x00 1676 str r1, [r0] 1677 1678/* Debug - UART console message */ 1679 ldr r0, =0x1e784000 1680 mov r1, #0x2E @ '.' 1681 str r1, [r0] 1682/* Debug - UART console message */ 1683 1684 clear_delay_timer 1685 /* Delay about 10us */ 1686 ldr r2, =0x0000000A @ Set Timer3 Reload = 10 us 1687 init_delay_timer 1688ddr_phy_init_delay_0: 1689 check_delay_timer 1690 bne ddr_phy_init_delay_0 1691 clear_delay_timer 1692 /* end delay 10us */ 1693 1694 ldr r0, =0x1e6e0060 @ Fire PHY Init 1695 mov r1, #0x05 1696 str r1, [r0] 1697 b ddr_phy_init_process 1698 1699ddr_phy_init_success: 1700 clear_delay_timer 1701 ldr r0, =0x1e6e0060 1702 mov r1, #0x06 1703 str r1, [r0] 1704 1705 ldr r0, =0x1e6e0120 1706 ldr r1, [r0] 1707 cmp r1, #0 1708 beq ddr3_phyinit_done 1709 cmp r1, #1 1710 beq ddr4_vref_phy_phyinit_done 1711 cmp r1, #2 1712 beq ddr4_vref_ddr_phyinit_done 1713#ifdef ASTMMC_DDR4_MANUAL_RPU 1714 cmp r1, #4 1715 beq ddr4_ron_phyinit_done 1716#endif 1717 b ddr4_phyinit_done 1718 1719 /******************************************** 1720 CBRTest 1721 ********************************************/ 1722cbr_test_start: 1723 ldr r0, =0x1e6e000c 1724 ldr r1, =0x00005C01 1725 str r1, [r0] 1726 ldr r0, =0x1e6e0074 1727 ldr r1, =0x0000FFFF @ test size = 64KB 1728 str r1, [r0] 1729 ldr r0, =0x1e6e007c 1730 ldr r1, =0xFF00FF00 1731 str r1, [r0] 1732 1733cbr_test_single: 1734 ldr r0, =0x1e6e0070 1735 ldr r1, =0x00000000 1736 str r1, [r0] 1737 ldr r1, =0x00000085 1738 str r1, [r0] 1739 ldr r3, =0x3000 1740 ldr r11, =0x50000 1741cbr_wait_engine_idle_0: 1742 subs r11, r11, #1 1743 beq cbr_test_fail 1744 ldr r2, [r0] 1745 tst r2, r3 @ D[12] = idle bit 1746 beq cbr_wait_engine_idle_0 1747 1748 ldr r0, =0x1e6e0070 @ read fail bit status 1749 ldr r3, =0x2000 1750 ldr r2, [r0] 1751 tst r2, r3 @ D[13] = fail bit 1752 bne cbr_test_fail 1753 1754cbr_test_burst: 1755 mov r1, #0x00 @ initialize loop index, r1 is loop index 1756cbr_test_burst_loop: 1757 ldr r0, =0x1e6e0070 1758 ldr r2, =0x00000000 1759 str r2, [r0] 1760 mov r2, r1, lsl #3 1761 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) 1762 str r2, [r0] 1763 ldr r3, =0x3000 1764 ldr r11, =0x20000 1765cbr_wait_engine_idle_1: 1766 subs r11, r11, #1 1767 beq cbr_test_fail 1768 ldr r2, [r0] 1769 tst r2, r3 @ D[12] = idle bit 1770 beq cbr_wait_engine_idle_1 1771 1772 ldr r0, =0x1e6e0070 @ read fail bit status 1773 ldr r3, =0x2000 1774 ldr r2, [r0] 1775 tst r2, r3 @ D[13] = fail bit 1776 bne cbr_test_fail 1777 1778 add r1, r1, #1 @ increase the test mode index 1779 cmp r1, #0x04 @ test 4 modes 1780 bne cbr_test_burst_loop 1781 1782 ldr r0, =0x1e6e0070 1783 ldr r1, =0x00000000 1784 str r1, [r0] 1785 mov r9, #0x1 1786 b cbr_test_pattern_end @ CBRTest() return(1) 1787 1788cbr_test_fail: 1789 ldr r0, =0x1e6e0070 1790 ldr r1, =0x00000000 1791 str r1, [r0] 1792 mov r9, #0x0 @ CBRTest() return(0) 1793 1794cbr_test_pattern_end: 1795 ldr r0, =0x1e6e000c 1796 ldr r1, =0x00000000 1797 str r1, [r0] 1798 ldr r0, =0x1e6e0120 1799 ldr r1, [r0] 1800 cmp r1, #1 1801 beq ddr4_vref_phy_cbrtest_done 1802 b ddr4_vref_ddr_cbrtest_done 1803 1804.LTORG 1805/****************************************************************************** 1806 Other features configuration 1807 *****************************************************************************/ 1808Calibration_End: 1809 /******************************* 1810 Check DRAM Size 1811 1Gb : 0x80000000 ~ 0x87FFFFFF 1812 2Gb : 0x80000000 ~ 0x8FFFFFFF 1813 4Gb : 0x80000000 ~ 0x9FFFFFFF 1814 8Gb : 0x80000000 ~ 0xBFFFFFFF 1815 *******************************/ 1816 ldr r0, =0x1e6e0004 1817 ldr r6, [r0] 1818 bic r6, r6, #0x00000003 @ record MCR04 1819 ldr r7, [r5, #ASTMMC_REGIDX_RFC] 1820 1821check_dram_size: 1822 ldr r0, =0xA0100000 1823 ldr r1, =0x41424344 1824 str r1, [r0] 1825 ldr r0, =0x90100000 1826 ldr r1, =0x35363738 1827 str r1, [r0] 1828 ldr r0, =0x88100000 1829 ldr r1, =0x292A2B2C 1830 str r1, [r0] 1831 ldr r0, =0x80100000 1832 ldr r1, =0x1D1E1F10 1833 str r1, [r0] 1834 ldr r0, =0xA0100000 1835 ldr r1, =0x41424344 1836 ldr r2, [r0] 1837 cmp r2, r1 @ == 8Gbit 1838 orreq r6, r6, #0x03 1839 moveq r7, r7, lsr #24 1840 mov r3, #0x38 @ '8' 1841 beq check_dram_size_end 1842 ldr r0, =0x90100000 1843 ldr r1, =0x35363738 1844 ldr r2, [r0] 1845 cmp r2, r1 @ == 4Gbit 1846 orreq r6, r6, #0x02 1847 moveq r7, r7, lsr #16 1848 mov r3, #0x34 @ '4' 1849 beq check_dram_size_end 1850 ldr r0, =0x88100000 1851 ldr r1, =0x292A2B2C 1852 ldr r2, [r0] 1853 cmp r2, r1 @ == 2Gbit 1854 orreq r6, r6, #0x01 1855 moveq r7, r7, lsr #8 1856 mov r3, #0x32 @ '2' 1857 beq check_dram_size_end 1858 mov r3, #0x31 @ '1' 1859 1860check_dram_size_end: 1861 ldr r0, =0x1e6e0004 1862 str r6, [r0] 1863 ldr r0, =0x1e6e0014 1864 ldr r1, [r0] 1865 bic r1, r1, #0x000000FF 1866 and r7, r7, #0xFF 1867 orr r1, r1, r7 1868 str r1, [r0] 1869 1870 /* Version Number */ 1871 ldr r0, =0x1e6e0004 1872 ldr r1, [r0] 1873 mov r2, #ASTMMC_INIT_VER 1874 orr r1, r1, r2, lsl #20 1875 str r1, [r0] 1876 1877 ldr r0, =0x1e6e0088 1878 ldr r1, =ASTMMC_INIT_DATE 1879 str r1, [r0] 1880 1881/* Debug - UART console message */ 1882 ldr r0, =0x1e784000 1883 mov r1, #0x2D @ '-' 1884 str r1, [r0] 1885 str r3, [r0] 1886 mov r1, #0x47 @ 'G' 1887 str r1, [r0] 1888 mov r1, #0x62 @ 'b' 1889 str r1, [r0] 1890 mov r1, #0x2D @ '-' 1891 str r1, [r0] 1892/* Debug - UART console message */ 1893 1894 /* Enable DRAM Cache */ 1895 ldr r0, =0x1e6e0004 1896 ldr r1, [r0] 1897 mov r2, #1 1898 orr r2, r1, r2, lsl #12 1899 str r2, [r0] 1900 ldr r3, =0x00080000 1901dram_cache_init: 1902 ldr r2, [r0] 1903 tst r2, r3 1904 beq dram_cache_init 1905 mov r2, #1 1906 orr r1, r1, r2, lsl #10 1907 str r1, [r0] 1908 1909 /* Set DRAM requests threshold */ 1910 ldr r0, =0x1e6e001c 1911 ldr r1, =0x00000008 1912 str r1, [r0] 1913 ldr r0, =0x1e6e0038 1914 ldr r1, =0xFFFFFF00 1915 str r1, [r0] 1916 1917 /******************************************** 1918 DDRTest 1919 ********************************************/ 1920ddr_test_start: 1921 ldr r0, =0x1e6e0074 1922 ldr r1, =0x0000FFFF @ test size = 64KB 1923 str r1, [r0] 1924 ldr r0, =0x1e6e007c 1925 ldr r1, =0xFF00FF00 1926 str r1, [r0] 1927 1928ddr_test_burst: 1929 mov r1, #0x00 @ initialize loop index, r1 is loop index 1930ddr_test_burst_loop: 1931 ldr r0, =0x1e6e0070 1932 ldr r2, =0x00000000 1933 str r2, [r0] 1934 mov r2, r1, lsl #3 1935 orr r2, r2, #0xC1 @ test command = 0xC1 | (datagen << 3) 1936 str r2, [r0] 1937 ldr r3, =0x3000 1938 ldr r11, =0x20000 1939ddr_wait_engine_idle_1: 1940 subs r11, r11, #1 1941 beq ddr_test_fail 1942 ldr r2, [r0] 1943 tst r2, r3 @ D[12] = idle bit 1944 beq ddr_wait_engine_idle_1 1945 1946 ldr r0, =0x1e6e0070 @ read fail bit status 1947 ldr r3, =0x2000 1948 ldr r2, [r0] 1949 tst r2, r3 @ D[13] = fail bit 1950 bne ddr_test_fail 1951 1952 add r1, r1, #1 @ increase the test mode index 1953 cmp r1, #0x01 @ test 1 modes 1954 bne ddr_test_burst_loop 1955 1956 ldr r0, =0x1e6e0070 1957 ldr r1, =0x00000000 1958 str r1, [r0] 1959 b set_scratch @ CBRTest() return(1) 1960 1961ddr_test_fail: 1962/* Debug - UART console message */ 1963 ldr r0, =0x1e784000 1964 mov r1, #0x46 @ 'F' 1965 str r1, [r0] 1966 mov r1, #0x61 @ 'a' 1967 str r1, [r0] 1968 mov r1, #0x69 @ 'i' 1969 str r1, [r0] 1970 mov r1, #0x6C @ 'l' 1971 str r1, [r0] 1972 mov r1, #0x0D @ '\r' 1973 str r1, [r0] 1974 mov r1, #0x0A @ '\n' 1975 str r1, [r0] 1976 ldr r0, =0x1e784014 1977wait_print_0: 1978 ldr r1, [r0] 1979 tst r1, #0x40 1980 beq wait_print_0 1981/* Debug - UART console message */ 1982 b reset_mmc 1983 1984set_scratch: 1985 /*Set Scratch register Bit 6 after ddr initial finished */ 1986 ldr r0, =0x1e6e2040 1987 ldr r1, [r0] 1988 orr r1, r1, #0x41 1989 str r1, [r0] 1990 1991/* Debug - UART console message */ 1992 ldr r0, =0x1e784000 1993 mov r1, #0x44 @ 'D' 1994 str r1, [r0] 1995 mov r1, #0x6F @ 'o' 1996 str r1, [r0] 1997 mov r1, #0x6E @ 'n' 1998 str r1, [r0] 1999 mov r1, #0x65 @ 'e' 2000 str r1, [r0] 2001 mov r1, #0x0D @ '\r' 2002 str r1, [r0] 2003 mov r1, #0x0A @ '\n' 2004 str r1, [r0] 2005/* Debug - UART console message */ 2006 2007 /* Enable VGA display */ 2008 ldr r0, =0x1e6e202c 2009 ldr r1, [r0] 2010 bic r1, r1, #0x40 2011 str r1, [r0] 2012 2013/* Debug - UART console message */ 2014 /* Print PHY timing information */ 2015 ldr r0, =0x1e784014 2016wait_print_1: 2017 ldr r1, [r0] 2018 tst r1, #0x40 2019 beq wait_print_1 2020 2021 ldr r0, =0x1e784000 2022 mov r1, #0x52 @ 'R' 2023 str r1, [r0] 2024 mov r1, #0x65 @ 'e' 2025 str r1, [r0] 2026 mov r1, #0x61 @ 'a' 2027 str r1, [r0] 2028 mov r1, #0x64 @ 'd' 2029 str r1, [r0] 2030 mov r1, #0x20 @ ' ' 2031 str r1, [r0] 2032 mov r1, #0x6D @ 'm' 2033 str r1, [r0] 2034 mov r1, #0x61 @ 'a' 2035 str r1, [r0] 2036 mov r1, #0x72 @ 'r' 2037 str r1, [r0] 2038 mov r1, #0x67 @ 'g' 2039 str r1, [r0] 2040 mov r1, #0x69 @ 'i' 2041 str r1, [r0] 2042 mov r1, #0x6E @ 'n' 2043 str r1, [r0] 2044 mov r1, #0x2D @ '-' 2045 str r1, [r0] 2046 mov r1, #0x44 @ 'D' 2047 str r1, [r0] 2048 mov r1, #0x4C @ 'L' 2049 str r1, [r0] 2050 mov r1, #0x3A @ ':' 2051 str r1, [r0] 2052 2053 ldr r0, =0x1e784014 2054wait_print_2: 2055 ldr r1, [r0] 2056 tst r1, #0x40 2057 beq wait_print_2 2058 2059 ldr r7, =0x000001FE @ divide by 510 2060 mov r8, #10 @ multiply by 10 2061 mov r9, #0 @ record violation 2062 ldr r0, =0x1e6e0004 2063 ldr r1, [r0] 2064 tst r1, #0x10 @ bit[4]=1 => DDR4 2065 movne r10, #0x9A @ DDR4 min = 0x99 (0.30) 2066 moveq r10, #0xB3 @ DDR3 min = 0xB3 (0.35) 2067print_DQL_eye_margin: 2068 ldr r0, =0x1e6e03d0 2069 ldr r2, [r0] 2070 and r2, r2, #0xFF 2071 cmp r2, r10 @ check violation 2072 movlt r9, #1 2073 ldr r0, =0x1e784000 2074 mov r1, #0x30 @ '0' 2075 str r1, [r0] 2076 mov r1, #0x2E @ '.' 2077 str r1, [r0] 2078 mov r3, #0x4 @ print 4 digits 2079print_DQL_div_loop: 2080 mul r2, r8, r2 2081 cmp r2, r7 2082 blt print_DQL_div_0 2083 mov r6, #0x0 2084print_DQL_div_digit: 2085 sub r2, r2, r7 2086 add r6, r6, #0x1 2087 cmp r2, r7 2088 bge print_DQL_div_digit 2089 b print_DQL_div_n 2090 2091print_DQL_div_0: 2092 mov r1, #0x30 @ '0' 2093 str r1, [r0] 2094 b print_DQL_next 2095print_DQL_div_n: 2096 add r1, r6, #0x30 @ print n 2097 str r1, [r0] 2098print_DQL_next: 2099 subs r3, r3, #1 2100 beq print_DQH_eye_margin 2101 cmp r2, #0x0 2102 beq print_DQH_eye_margin 2103 b print_DQL_div_loop 2104 2105print_DQH_eye_margin: 2106 mov r1, #0x2F @ '/' 2107 str r1, [r0] 2108 mov r1, #0x44 @ 'D' 2109 str r1, [r0] 2110 mov r1, #0x48 @ 'H' 2111 str r1, [r0] 2112 mov r1, #0x3A @ ':' 2113 str r1, [r0] 2114 2115 ldr r0, =0x1e784014 2116wait_print_3: 2117 ldr r1, [r0] 2118 tst r1, #0x40 2119 beq wait_print_3 2120 2121 ldr r0, =0x1e6e03d0 2122 ldr r2, [r0] 2123 mov r2, r2, lsr #8 2124 and r2, r2, #0xFF 2125 cmp r2, r10 @ check violation 2126 movlt r9, #1 2127 ldr r0, =0x1e784000 2128 mov r1, #0x30 @ '0' 2129 str r1, [r0] 2130 mov r1, #0x2E @ '.' 2131 str r1, [r0] 2132 mov r3, #0x4 @ print 4 digits 2133print_DQH_div_loop: 2134 mul r2, r8, r2 2135 cmp r2, r7 2136 blt print_DQH_div_0 2137 mov r6, #0x0 2138print_DQH_div_digit: 2139 sub r2, r2, r7 2140 add r6, r6, #0x1 2141 cmp r2, r7 2142 bge print_DQH_div_digit 2143 b print_DQH_div_n 2144 2145print_DQH_div_0: 2146 mov r1, #0x30 @ '0' 2147 str r1, [r0] 2148 b print_DQH_next 2149print_DQH_div_n: 2150 add r1, r6, #0x30 @ print n 2151 str r1, [r0] 2152print_DQH_next: 2153 subs r3, r3, #1 2154 beq print_DQ_eye_margin_last 2155 cmp r2, #0x0 2156 beq print_DQ_eye_margin_last 2157 b print_DQH_div_loop 2158 2159print_DQ_eye_margin_last: 2160 mov r1, #0x20 @ ' ' 2161 str r1, [r0] 2162 mov r1, #0x43 @ 'C' 2163 str r1, [r0] 2164 mov r1, #0x4B @ 'K' 2165 str r1, [r0] 2166 2167 ldr r0, =0x1e6e0004 2168 ldr r1, [r0] 2169 tst r1, #0x10 @ bit[4]=1 => DDR4 2170 movne r10, #0x30 @ DDR4 min = 0.30 2171 moveq r10, #0x35 @ DDR4 min = 0.35 2172 2173 ldr r0, =0x1e784014 2174wait_print_4: 2175 ldr r1, [r0] 2176 tst r1, #0x40 2177 beq wait_print_4 2178 2179 ldr r0, =0x1e784000 2180 mov r1, #0x20 @ ' ' 2181 str r1, [r0] 2182 mov r1, #0x28 @ '(' 2183 str r1, [r0] 2184 mov r1, #0x6D @ 'm' 2185 str r1, [r0] 2186 mov r1, #0x69 @ 'i' 2187 str r1, [r0] 2188 mov r1, #0x6E @ 'n' 2189 str r1, [r0] 2190 mov r1, #0x3A @ ':' 2191 str r1, [r0] 2192 mov r1, #0x30 @ '0' 2193 str r1, [r0] 2194 mov r1, #0x2E @ '.' 2195 str r1, [r0] 2196 mov r1, #0x33 @ '3' 2197 str r1, [r0] 2198 str r10, [r0] 2199 mov r1, #0x29 @ ')' 2200 str r1, [r0] 2201 2202 cmp r9, #0 2203 beq print_DQ_margin_last 2204 mov r1, #0x20 @ ' ' 2205 str r1, [r0] 2206 ldr r0, =0x1e784014 2207wait_print_5: 2208 ldr r1, [r0] 2209 tst r1, #0x40 2210 beq wait_print_5 2211 2212 ldr r0, =0x1e784000 2213 mov r1, #0x57 @ 'W' 2214 str r1, [r0] 2215 mov r1, #0x61 @ 'a' 2216 str r1, [r0] 2217 mov r1, #0x72 @ 'r' 2218 str r1, [r0] 2219 mov r1, #0x6E @ 'n' 2220 str r1, [r0] 2221 mov r1, #0x69 @ 'i' 2222 str r1, [r0] 2223 mov r1, #0x6E @ 'n' 2224 str r1, [r0] 2225 mov r1, #0x67 @ 'g' 2226 str r1, [r0] 2227 mov r1, #0x3A @ ':' 2228 str r1, [r0] 2229 mov r1, #0x20 @ ' ' 2230 str r1, [r0] 2231 mov r1, #0x4D @ 'M' 2232 str r1, [r0] 2233 mov r1, #0x61 @ 'a' 2234 str r1, [r0] 2235 mov r1, #0x72 @ 'r' 2236 str r1, [r0] 2237 mov r1, #0x67 @ 'g' 2238 str r1, [r0] 2239 mov r1, #0x69 @ 'i' 2240 str r1, [r0] 2241 mov r1, #0x6E @ 'n' 2242 str r1, [r0] 2243 ldr r0, =0x1e784014 2244wait_print_6: 2245 ldr r1, [r0] 2246 tst r1, #0x40 2247 beq wait_print_6 2248 ldr r0, =0x1e784000 2249 mov r1, #0x20 @ ' ' 2250 str r1, [r0] 2251 mov r1, #0x74 @ 't' 2252 str r1, [r0] 2253 mov r1, #0x6F @ 'o' 2254 str r1, [r0] 2255 mov r1, #0x6F @ 'o' 2256 str r1, [r0] 2257 mov r1, #0x20 @ ' ' 2258 str r1, [r0] 2259 mov r1, #0x73 @ 's' 2260 str r1, [r0] 2261 mov r1, #0x6D @ 'm' 2262 str r1, [r0] 2263 mov r1, #0x61 @ 'a' 2264 str r1, [r0] 2265 mov r1, #0x6C @ 'l' 2266 str r1, [r0] 2267 mov r1, #0x6C @ 'l' 2268 str r1, [r0] 2269 2270print_DQ_margin_last: 2271 mov r1, #0x0D @ '\r' 2272 str r1, [r0] 2273 mov r1, #0x0A @ '\n' 2274 str r1, [r0] 2275/* Debug - UART console message */ 2276 2277platform_exit: 2278#ifdef CONFIG_DRAM_ECC 2279 ldr r0, =0x1e6e0004 2280 ldr r2, =0x00000880 @ add cache range control, 2016.09.02 2281 ldr r1, [r0] 2282 orr r1, r1, r2 2283 str r1, [r0] 2284 2285 ldr r0, =0x1e6e0054 2286 ldr r1, =CONFIG_DRAM_ECC_SIZE /* ECC protected memory size */ 2287 str r1, [r0] 2288 2289 ldr r0, =0x1e6e007C 2290 ldr r1, =0x00000000 2291 str r1, [r0] 2292 ldr r0, =0x1e6e0074 2293 str r1, [r0] 2294 2295 ldr r0, =0x1e6e0070 2296 ldr r1, =0x00000221 2297 str r1, [r0] 2298 2299 ldr r2, =0x00001000 2300ECC_Init_Flag: 2301 ldr r1, [r0] 2302 tst r1, r2 @ D[12] = 1, Done 2303 beq ECC_Init_Flag 2304 2305 ldr r1, =0x00000000 2306 str r1, [r0] 2307 2308 ldr r0, =0x1e6e0050 2309 ldr r1, =0x80000000 2310 str r1, [r0] 2311 2312 ldr r0, =0x1e6e0050 2313 ldr r1, =0x00000000 2314 str r1, [r0] 2315 2316 ldr r0, =0x1e6e0070 2317 ldr r1, =0x00000400 @ Enable ECC auto-scrubbing 2318 str r1, [r0] 2319#endif 2320 2321/****************************************************************************** 2322 SPI Timing Calibration 2323 ******************************************************************************/ 2324 mov r2, #0x0 2325 mov r6, #0x0 2326 mov r7, #0x0 2327 init_spi_checksum 2328spi_checksum_wait_0: 2329 ldr r1, [r0] 2330 tst r1, r2 2331 beq spi_checksum_wait_0 2332 ldr r0, =0x1e620090 2333 ldr r5, [r0] @ record golden checksum 2334 ldr r0, =0x1e620080 2335 mov r1, #0x0 2336 str r1, [r0] 2337 2338 ldr r0, =0x1e620010 @ set to fast read mode 2339 ldr r1, =0x000B0041 2340 str r1, [r0] 2341 2342 ldr r6, =0x00F7E6D0 @ Init spiclk loop 2343 mov r8, #0x0 @ Init delay record 2344 2345spi_cbr_next_clkrate: 2346 mov r6, r6, lsr #0x4 2347 cmp r6, #0x0 2348 beq spi_cbr_end 2349 2350 mov r7, #0x0 @ Init delay loop 2351 mov r8, r8, lsl #4 2352 2353spi_cbr_next_delay_s: 2354 mov r2, #0x8 2355 init_spi_checksum 2356spi_checksum_wait_1: 2357 ldr r1, [r0] 2358 tst r1, r2 2359 beq spi_checksum_wait_1 2360 ldr r0, =0x1e620090 2361 ldr r2, [r0] @ read checksum 2362 ldr r0, =0x1e620080 2363 mov r1, #0x0 2364 str r1, [r0] 2365 cmp r2, r5 2366 bne spi_cbr_next_delay_e 2367 2368 mov r2, #0x0 2369 init_spi_checksum 2370spi_checksum_wait_2: 2371 ldr r1, [r0] 2372 tst r1, r2 2373 beq spi_checksum_wait_2 2374 ldr r0, =0x1e620090 2375 ldr r2, [r0] @ read checksum 2376 ldr r0, =0x1e620080 2377 mov r1, #0x0 2378 str r1, [r0] 2379 cmp r2, r5 2380 bne spi_cbr_next_delay_e 2381 2382 orr r8, r8, r7 @ record passed delay 2383 b spi_cbr_next_clkrate 2384 2385spi_cbr_next_delay_e: 2386 add r7, r7, #0x1 2387 cmp r7, #0x6 2388 blt spi_cbr_next_delay_s 2389 b spi_cbr_next_clkrate 2390 2391spi_cbr_end: 2392 ldr r0, =0x1e620094 2393 str r8, [r0] 2394 ldr r0, =0x1e620010 2395 mov r1, #0x0 2396 str r1, [r0] 2397 2398/****************************************************************************** 2399 Miscellaneous Setting 2400 ******************************************************************************/ 2401 /* Set UART DMA as AHB high priority master */ 2402 ldr r0, =0x1e600000 2403 ldr r1, =0xAEED1A03 2404 str r1, [r0] 2405 2406 ldr r0, =0x1e600080 2407 ldr r2, =0x100 2408 ldr r1, [r0] 2409 orr r1, r1, r2 2410 str r1, [r0] 2411 2412 /* Enable UART3/4 clock and disable LHCLK */ 2413 ldr r0, =0x1e6e200c 2414 ldr r1, [r0] 2415 ldr r2, =0xF9FFFFFF 2416 and r1, r1, r2 2417 ldr r2, =0x10000000 2418 orr r1, r1, r2 2419 str r1, [r0] 2420 2421 ldr r0, =0x1e6e2008 @ Set Video ECLK phase 2422 ldr r1, [r0] 2423 ldr r2, =0x0ffffff3 2424 and r1, r1, r2 2425 str r1, [r0] 2426 2427 ldr r0, =0x1e6e2004 @ Enable JTAG Master, solve ARM stucked by JTAG issue 2428 ldr r1, [r0] 2429 bic r1, r1, #0x00400000 2430 str r1, [r0] 2431 2432/****************************************************************************** 2433 Configure MAC timing 2434 ******************************************************************************/ 2435 /* Enable D2PLL and set to 250MHz */ 2436 ldr r0, =0x1e6e213c 2437 ldr r1, =0x00000585 @ Reset D2PLL 2438 str r1, [r0] 2439 2440 ldr r0, =0x1e6e202c 2441 ldr r1, [r0] 2442 bic r1, r1, #0x10 @ Enable D2PLL 2443 ldr r2, =0x00200000 @ Set CRT = 40MHz 2444 orr r1, r1, r2 2445 str r1, [r0] 2446 2447 ldr r2, =0x8E00A17C @ Set to 250MHz 2448 2449 ldr r0, =0x1e6e2070 @ Check CLKIN = 25MHz 2450 ldr r1, [r0] 2451 mov r1, r1, lsr #23 2452 tst r1, #0x01 2453 beq set_D2PLL 2454 ldr r2, =0x8E00A177 2455 2456set_D2PLL: 2457 ldr r0, =0x1e6e201c 2458 str r2, [r0] 2459 ldr r0, =0x1e6e213c @ Enable D2PLL 2460 ldr r1, =0x00000580 2461 str r1, [r0] 2462 2463 ldr r0, =0x1e6e204c 2464 ldr r1, [r0] 2465 bic r1, r1, #0xFF0000 2466 ldr r2, =0x00040000 @ Set divider ratio 2467 orr r1, r1, r2 2468 str r1, [r0] 2469 2470 ldr r0, =0x1e6e2048 @ Set MAC interface delay timing = 1G 2471 ldr r1, =0x80082208 @ Select internal 125MHz 2472 str r1, [r0] 2473 ldr r0, =0x1e6e20b8 @ Set MAC interface delay timing = 100M 2474 str r1, [r0] 2475 ldr r0, =0x1e6e20bc @ Set MAC interface delay timing = 10M 2476 str r1, [r0] 2477 2478 ldr r0, =0x1e6e2070 @ Set MAC AHB bus clock 2479 ldr r1, [r0] 2480 mov r2, #0x04 @ Default RMII, set MHCLK = HPLL/10 2481 tst r1, #0xC0 2482 movne r2, #0x02 @ if RGMII, set MHCLK = HPLL/6 2483 ldr r0, =0x1e6e2008 2484 ldr r1, [r0] 2485 bic r1, r1, #0x00070000 2486 orr r1, r1, r2, lsl #16 2487 str r1, [r0] 2488 2489 ldr r0, =0x1e6e21dc @ Set MAC duty 2490 ldr r1, =0x00666400 2491 str r1, [r0] 2492 2493 ldr r0, =0x1e6e2090 @ Enable MAC interface pull low 2494 ldr r1, [r0] 2495 bic r1, r1, #0x0000F000 2496 bic r1, r1, #0x20000000 @ Set USB portA as Device mode 2497 str r1, [r0] 2498 2499/* Test - DRAM initial time */ 2500 ldr r0, =0x1e782040 2501 ldr r1, [r0] 2502 ldr r0, =0xFFFFFFFF 2503 sub r1, r0, r1 2504 ldr r0, =0x1e6e008c 2505 str r1, [r0] 2506 ldr r0, =0x1e78203c 2507 ldr r1, =0x0000F000 2508 str r1, [r0] 2509/* Test - DRAM initial time */ 2510 2511 ldr r0, =0x1e6e0000 @ disable MMC password 2512 mov r1, #0x0 2513 str r1, [r0] 2514 2515 /* Disable Timer separate mode */ 2516 ldr r0, =0x1e782038 2517 ldr r1, =0xEA 2518 str r1, [r0] 2519 2520 /* restore lr */ 2521 mov lr, r4 2522 2523 /* back to arch calling code */ 2524 mov pc, lr 2525 2526