1 // SPDX-License-Identifier: GPL-2.0+
2 #include <common.h>
3 #include <dm.h>
4 #include <ram.h>
5 #include <timer.h>
6 #include <asm/io.h>
7 #include <asm/arch/platform.h>
8 #include <asm/arch/scu_ast2400.h>
9 #include <asm/arch/timer.h>
10 #include <linux/err.h>
11 #include <dm/uclass.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 #define AST_LPC_HICR5 0x080
16 # define LPC_HICR5_ENFWH BIT(10)
17 #define AST_LPC_HICRB 0x100
18 # define LPC_HICRB_SIO_ILPC2AHB_DIS BIT(6)
19 
20 #define AST_SDMC_PROTECT 0x00
21 # define SDRAM_UNLOCK_KEY 0xfc600309
22 #define AST_SDMC_GFX_PROT 0x08
23 # define SDMC_GFX_PROT_VGA_CURSOR BIT(0)
24 # define SDMC_GFX_PROT_VGA_CG_READ BIT(1)
25 # define SDMC_GFX_PROT_VGA_ASCII_READ BIT(2)
26 # define SDMC_GFX_PROT_VGA_CRT BIT(3)
27 # define SDMC_GFX_PROT_PCIE BIT(16)
28 # define SDMC_GFX_PROT_XDMA BIT(17)
29 
30 static void isolate_bmc(void)
31 {
32 	bool sdmc_unlocked;
33 	u32 val;
34 
35 	/* iLPC2AHB */
36 #if !defined(CONFIG_ASPEED_ENABLE_SUPERIO)
37 	val = readl(ASPEED_HW_STRAP1);
38 	val |= SCU_HWSTRAP_LPC_SIO_DEC_DIS;
39 	writel(val, ASPEED_HW_STRAP1);
40 #endif
41 
42 	val = readl(ASPEED_LPC_CTRL + AST_LPC_HICRB);
43 	val |= LPC_HICRB_SIO_ILPC2AHB_DIS;
44 	writel(val, ASPEED_LPC_CTRL + AST_LPC_HICRB);
45 
46 	/* P2A, PCIe BMC */
47 	val = readl(ASPEED_PCIE_CONFIG_SET);
48 	val &= ~(SCU_PCIE_CONFIG_SET_BMC_DMA
49 	         | SCU_PCIE_CONFIG_SET_BMC_MMIO
50 	         | SCU_PCIE_CONFIG_SET_BMC_EN
51 	         | SCU_PCIE_CONFIG_SET_VGA_MMIO);
52 	writel(val, ASPEED_PCIE_CONFIG_SET);
53 
54 	/* X-DMA */
55 	sdmc_unlocked = readl(ASPEED_SDRAM_CTRL + AST_SDMC_PROTECT);
56 	if (!sdmc_unlocked)
57 		writel(SDRAM_UNLOCK_KEY, ASPEED_SDRAM_CTRL + AST_SDMC_PROTECT);
58 
59 	val = readl(ASPEED_SDRAM_CTRL + AST_SDMC_GFX_PROT);
60 	val |= (SDMC_GFX_PROT_VGA_CURSOR
61 	        | SDMC_GFX_PROT_VGA_CG_READ
62 	        | SDMC_GFX_PROT_VGA_ASCII_READ
63 	        | SDMC_GFX_PROT_VGA_CRT
64 	        | SDMC_GFX_PROT_PCIE
65 	        | SDMC_GFX_PROT_XDMA);
66 	writel(val, ASPEED_SDRAM_CTRL + AST_SDMC_GFX_PROT);
67 
68 	if (!sdmc_unlocked)
69 		writel(~SDRAM_UNLOCK_KEY, ASPEED_SDRAM_CTRL + AST_SDMC_PROTECT);
70 
71 	/* LPC2AHB */
72 	val = readl(ASPEED_LPC_CTRL + AST_LPC_HICR5);
73 	val &= ~LPC_HICR5_ENFWH;
74 	writel(val, ASPEED_LPC_CTRL + AST_LPC_HICR5);
75 }
76 
77 __weak int board_init(void)
78 {
79 	isolate_bmc();
80 
81 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
82 
83 	return 0;
84 }
85 
86 #define SDMC_CONFIG_VRAM_GET(x)         ((x >> 2) & 0x3)
87 #define SDMC_CONFIG_MEM_GET(x)          (x & 0x3)
88 
89 static const u32 ast2400_dram_table[] = {
90 	0x04000000,     //64MB
91 	0x08000000,     //128MB
92 	0x10000000, 	//256MB
93 	0x20000000,     //512MB
94 };
95 
96 u32
97 ast_sdmc_get_mem_size(void)
98 {
99 	u32 size = 0;
100 	u32 size_conf = SDMC_CONFIG_MEM_GET(readl(0x1e6e0004));
101 
102 	size = ast2400_dram_table[size_conf];
103 
104 	return size;
105 }
106 
107 
108 static const u32 aspeed_vram_table[] = {
109 	0x00800000,     //8MB
110 	0x01000000,     //16MB
111 	0x02000000,     //32MB
112 	0x04000000,     //64MB
113 };
114 
115 u32
116 ast_sdmc_get_vram_size(void)
117 {
118 	u32 size_conf = SDMC_CONFIG_VRAM_GET(readl(0x1e6e0004));
119 	return aspeed_vram_table[size_conf];
120 }
121 
122 __weak int dram_init(void)
123 {
124 #if 0
125 	struct udevice *dev;
126 	struct ram_info ram;
127 	int ret;
128 
129 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
130 	if (ret) {
131 		debug("DRAM FAIL1\r\n");
132 		return ret;
133 	}
134 
135 	ret = ram_get_info(dev, &ram);
136 	if (ret) {
137 		debug("DRAM FAIL2\r\n");
138 		return ret;
139 	}
140 
141 	gd->ram_size = ram.size;
142 #else
143 	u32 vga = ast_sdmc_get_vram_size();
144 	u32 dram = ast_sdmc_get_mem_size();
145 	gd->ram_size = (dram - vga);
146 #endif
147 	return 0;
148 }
149