1if ARCH_ASPEED 2 3config SYS_ARCH 4 default "arm" 5 6config SYS_SOC 7 default "aspeed" 8 9config SYS_TEXT_BASE 10 default 0x00000000 11 12choice 13 prompt "Aspeed SoC select" 14 depends on ARCH_ASPEED 15 default ASPEED_AST2500 16 17config ASPEED_AST2400 18 bool "Support Aspeed AST2400 SoC" 19 select CPU_ARM926EJS 20 help 21 The Aspeed AST2400 is a ARM-based SoC with arm926ejs CPU. 22 It is used as Board Management Controller on many server boards, 23 which is enabled by support of LPC and eSPI peripherals. 24 25config ASPEED_AST2500 26 bool "Support Aspeed AST2500 SoC" 27 select CPU_ARM1176 28 select SUPPORT_SPL 29 help 30 The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. 31 It is used as Board Management Controller on many server boards, 32 which is enabled by support of LPC and eSPI peripherals. 33 34config ASPEED_AST2600 35 bool "Support Aspeed AST2600 SoC" 36 select CPU_V7A 37 select CPU_V7_HAS_NONSEC 38 select ARCH_SUPPORT_PSCI 39 select SYS_ARCH_TIMER 40 select SUPPORT_SPL 41 select ENABLE_ARM_SOC_BOOT0_HOOK 42 help 43 The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. 44 It is used as Board Management Controller on many server boards, 45 which is enabled by support of LPC and eSPI peripherals. 46endchoice 47 48config ASPEED_PALLADIUM 49 bool "Aspeed palladium for simulation" 50 default n 51 help 52 Say Y here to enable palladium build for simulation. 53 54 This is mainly for internal verification and investigation 55 on HW design. If not sure, say N. 56 57config ASPEED_SSP_RERV_MEM 58 hex "Reserve memory for SSP" 59 default 0x0 60 help 61 The size in bytes of reserve memory for ASPEED SoC SSP run. 62 63config ASPEED_DEFAULT_SPI_FREQUENCY 64 bool "Using default SPI clock frequency" 65 default n 66 help 67 Using default SPI clock frequency during 68 early booting up progress. 69 70source "arch/arm/mach-aspeed/ast2400/Kconfig" 71source "arch/arm/mach-aspeed/ast2500/Kconfig" 72source "arch/arm/mach-aspeed/ast2600/Kconfig" 73 74endif 75