1if ARCH_ASPEED 2 3config SYS_ARCH 4 default "arm" 5 6config SYS_SOC 7 default "aspeed" 8 9config SYS_TEXT_BASE 10 default 0x00000000 11 12choice 13 prompt "Aspeed SoC select" 14 depends on ARCH_ASPEED 15 default ASPEED_AST2500 16 17config ASPEED_AST2400 18 bool "Support Aspeed AST2400 SoC" 19 select CPU_ARM926EJS 20 help 21 The Aspeed AST2400 is a ARM-based SoC with arm926ejs CPU. 22 It is used as Board Management Controller on many server boards, 23 which is enabled by support of LPC and eSPI peripherals. 24 25config ASPEED_AST2500 26 bool "Support Aspeed AST2500 SoC" 27 select CPU_ARM1176 28 select SUPPORT_SPL 29 help 30 The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU. 31 It is used as Board Management Controller on many server boards, 32 which is enabled by support of LPC and eSPI peripherals. 33 34config ASPEED_AST2600 35 bool "Support Aspeed AST2600 SoC" 36 select CPU_V7A 37 select CPU_V7_HAS_NONSEC 38 select ARCH_SUPPORT_PSCI 39 select SYS_ARCH_TIMER 40 select SUPPORT_SPL 41 select ENABLE_ARM_SOC_BOOT0_HOOK 42 help 43 The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. 44 It is used as Board Management Controller on many server boards, 45 which is enabled by support of LPC and eSPI peripherals. 46endchoice 47 48config ASPEED_ALLOW_DANGEROUS_BACKDOORS 49 bool "Expose options enabling dangerous Aspeed hardware backdoors" 50 help 51 This option exposes configuration settings that create 52 critical security vulnerabilities by enabling dangerous 53 hardware backdoors in Aspeed BMCs. Enable it only if 54 absolutely required for a specific system or for debugging 55 during development. 56 57if ASPEED_ALLOW_DANGEROUS_BACKDOORS 58 59config ASPEED_ENABLE_SUPERIO 60 bool "Enable built-in AST2x00 Super I/O hardware" 61 depends on ASPEED_AST2400 || ASPEED_AST2500 62 help 63 The Aspeed AST2400 and AST2500 include a built-in Super I/O 64 device that is normally disabled; say Y here to enable it. 65 66 WARNING: this has serious security implications: it grants 67 the host read access to the BMC's entire address space. 68 This should thus be left disabled unless required by a 69 specific system. 70 71config ASPEED_ENABLE_DEBUG_UART 72 bool "Enable AST2500 hardware debug UART" 73 depends on ASPEED_AST2500 74 help 75 The Aspeed AST2500 include a hardware-supported, UART-based 76 debug interface that is normally disabled; say Y here to 77 enable it. 78 79 Note that this has security implications: the debug UART 80 provides read/write access to the BMC's entire address 81 space. This should thus be left disabled on production 82 systems, but may be useful to enable for debugging during 83 development. 84 85endif 86 87config ASPEED_PALLADIUM 88 bool "Aspeed palladium for simulation" 89 default n 90 help 91 Say Y here to enable palladium build for simulation. 92 93 This is mainly for internal verification and investigation 94 on HW design. If not sure, say N. 95 96config ASPEED_SSP_RERV_MEM 97 hex "Reserve memory for SSP" 98 default 0x0 99 help 100 The size in bytes of reserve memory for ASPEED SoC SSP run. 101 102config ASPEED_DEFAULT_SPI_FREQUENCY 103 bool "Using default SPI clock frequency" 104 default n 105 help 106 Using default SPI clock frequency during 107 early booting up progress. 108 109source "arch/arm/mach-aspeed/ast2400/Kconfig" 110source "arch/arm/mach-aspeed/ast2500/Kconfig" 111source "arch/arm/mach-aspeed/ast2600/Kconfig" 112 113endif 114